Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_070600                                 07-Aug-2020 12:05                7875
FPDL13_DWMZ_080600                                 08-Aug-2020 07:50                2600
FPDL13_DWMZ_090600                                 09-Aug-2020 07:17                4364
SXDL31_DWAV_071800                                 07-Aug-2020 16:27                6966
SXDL31_DWAV_080800                                 08-Aug-2020 06:54                7337
SXDL31_DWAV_081800                                 08-Aug-2020 16:36                7502
SXDL31_DWAV_090800                                 09-Aug-2020 07:41                7664
SXDL33_DWAV_070000                                 07-Aug-2020 09:13                8936
SXDL33_DWAV_080000                                 08-Aug-2020 09:33                7333
ber01-FWDL39_DWMS_071230-2008071230-dsw--0-ia5     07-Aug-2020 11:55                1147
ber01-FWDL39_DWMS_081230-2008081230-dsw--0-ia5     08-Aug-2020 12:06                1229
ber01-VHDL13_DWEH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:28                2102
ber01-VHDL13_DWEH_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:28                2119
ber01-VHDL13_DWEH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:28                2049
ber01-VHDL13_DWEH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:28                2373
ber01-VHDL13_DWEH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:58                2311
ber01-VHDL13_DWEH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:28                2311
ber01-VHDL13_DWEH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:28                2287
ber01-VHDL13_DWEH_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:28                2735
ber01-VHDL13_DWEH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:28                2575
ber01-VHDL13_DWEH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:28                2946
ber01-VHDL13_DWEH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:58                3030
ber01-VHDL13_DWEH_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                3009
ber01-VHDL13_DWEH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:28                3080
ber01-VHDL13_DWHG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2103
ber01-VHDL13_DWHG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2030
ber01-VHDL13_DWHG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2138
ber01-VHDL13_DWHG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2155
ber01-VHDL13_DWHG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2176
ber01-VHDL13_DWHG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2148
ber01-VHDL13_DWHG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2414
ber01-VHDL13_DWHG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2960
ber01-VHDL13_DWHG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2939
ber01-VHDL13_DWHG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2715
ber01-VHDL13_DWHH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2023
ber01-VHDL13_DWHH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1988
ber01-VHDL13_DWHH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2137
ber01-VHDL13_DWHH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2128
ber01-VHDL13_DWHH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2160
ber01-VHDL13_DWHH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2122
ber01-VHDL13_DWHH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2138
ber01-VHDL13_DWHH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2578
ber01-VHDL13_DWHH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2578
ber01-VHDL13_DWHH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2300
ber01-VHDL13_DWLG_070933-2008070933-dsw--0-ia5     07-Aug-2020 09:33                1958
ber01-VHDL13_DWLG_071033-2008071033-dsw--0-ia5     07-Aug-2020 10:33                1952
ber01-VHDL13_DWLG_071133-2008071133-dsw--0-ia5     07-Aug-2020 11:33                1952
ber01-VHDL13_DWLG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                1891
ber01-VHDL13_DWLG_071333-2008071333-dsw--0-ia5     07-Aug-2020 13:33                1883
ber01-VHDL13_DWLG_071433-2008071433-dsw--0-ia5     07-Aug-2020 14:33                1883
ber01-VHDL13_DWLG_071533-2008071533-dsw--0-ia5     07-Aug-2020 15:33                1883
ber01-VHDL13_DWLG_071633-2008071633-dsw--0-ia5     07-Aug-2020 16:33                1883
ber01-VHDL13_DWLG_071733-2008071733-dsw--0-ia5     07-Aug-2020 17:33                1755
ber01-VHDL13_DWLG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1690
ber01-VHDL13_DWLG_071933-2008071933-dsw--0-ia5     07-Aug-2020 19:33                1718
ber01-VHDL13_DWLG_072033-2008072033-dsw--0-ia5     07-Aug-2020 20:33                1718
ber01-VHDL13_DWLG_080033-2008080033-dsw--0-ia5     08-Aug-2020 00:33                1878
ber01-VHDL13_DWLG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1869
ber01-VHDL13_DWLG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1842
ber01-VHDL13_DWLG_080533-2008080533-dsw--0-ia5     08-Aug-2020 05:33                1870
ber01-VHDL13_DWLG_080633-2008080633-dsw--0-ia5     08-Aug-2020 06:33                1870
ber01-VHDL13_DWLG_080733-2008080733-dsw--0-ia5     08-Aug-2020 07:33                1870
ber01-VHDL13_DWLG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1977
ber01-VHDL13_DWLG_080933-2008080933-dsw--0-ia5     08-Aug-2020 09:33                2008
ber01-VHDL13_DWLG_081033-2008081033-dsw--0-ia5     08-Aug-2020 10:33                2040
ber01-VHDL13_DWLG_081133-2008081133-dsw--0-ia5     08-Aug-2020 11:33                2040
ber01-VHDL13_DWLG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                1942
ber01-VHDL13_DWLG_081333-2008081333-dsw--0-ia5     08-Aug-2020 13:33                2073
ber01-VHDL13_DWLG_081433-2008081433-dsw--0-ia5     08-Aug-2020 14:33                2073
ber01-VHDL13_DWLG_081533-2008081533-dsw--0-ia5     08-Aug-2020 15:33                2073
ber01-VHDL13_DWLG_081633-2008081633-dsw--0-ia5     08-Aug-2020 16:33                2073
ber01-VHDL13_DWLG_081733-2008081733-dsw--0-ia5     08-Aug-2020 17:33                2098
ber01-VHDL13_DWLG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2115
ber01-VHDL13_DWLG_081933-2008081933-dsw--0-ia5     08-Aug-2020 19:33                2143
ber01-VHDL13_DWLG_082033-2008082033-dsw--0-ia5     08-Aug-2020 20:33                2143
ber01-VHDL13_DWLG_090033-2008090033-dsw--0-ia5     09-Aug-2020 00:33                2163
ber01-VHDL13_DWLG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2146
ber01-VHDL13_DWLG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2118
ber01-VHDL13_DWLG_090533-2008090533-dsw--0-ia5     09-Aug-2020 05:33                2088
ber01-VHDL13_DWLG_090633-2008090633-dsw--0-ia5     09-Aug-2020 06:33                2088
ber01-VHDL13_DWLG_090733-2008090733-dsw--0-ia5     09-Aug-2020 07:33                2088
ber01-VHDL13_DWLG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2057
ber01-VHDL13_DWLH_070933-2008070933-dsw--0-ia5     07-Aug-2020 09:33                1888
ber01-VHDL13_DWLH_071033-2008071033-dsw--0-ia5     07-Aug-2020 10:33                1882
ber01-VHDL13_DWLH_071133-2008071133-dsw--0-ia5     07-Aug-2020 11:33                1882
ber01-VHDL13_DWLH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                1828
ber01-VHDL13_DWLH_071333-2008071333-dsw--0-ia5     07-Aug-2020 13:33                1816
ber01-VHDL13_DWLH_071433-2008071433-dsw--0-ia5     07-Aug-2020 14:33                1816
ber01-VHDL13_DWLH_071533-2008071533-dsw--0-ia5     07-Aug-2020 15:33                1816
ber01-VHDL13_DWLH_071633-2008071633-dsw--0-ia5     07-Aug-2020 16:33                1816
ber01-VHDL13_DWLH_071733-2008071733-dsw--0-ia5     07-Aug-2020 17:33                1696
ber01-VHDL13_DWLH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1631
ber01-VHDL13_DWLH_071933-2008071933-dsw--0-ia5     07-Aug-2020 19:33                1659
ber01-VHDL13_DWLH_072033-2008072033-dsw--0-ia5     07-Aug-2020 20:33                1659
ber01-VHDL13_DWLH_080033-2008080033-dsw--0-ia5     08-Aug-2020 00:33                1801
ber01-VHDL13_DWLH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1790
ber01-VHDL13_DWLH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1765
ber01-VHDL13_DWLH_080533-2008080533-dsw--0-ia5     08-Aug-2020 05:33                1793
ber01-VHDL13_DWLH_080633-2008080633-dsw--0-ia5     08-Aug-2020 06:33                1793
ber01-VHDL13_DWLH_080733-2008080733-dsw--0-ia5     08-Aug-2020 07:33                1793
ber01-VHDL13_DWLH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1882
ber01-VHDL13_DWLH_080933-2008080933-dsw--0-ia5     08-Aug-2020 09:33                1910
ber01-VHDL13_DWLH_081033-2008081033-dsw--0-ia5     08-Aug-2020 10:33                1942
ber01-VHDL13_DWLH_081133-2008081133-dsw--0-ia5     08-Aug-2020 11:33                1942
ber01-VHDL13_DWLH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                1848
ber01-VHDL13_DWLH_081300_COR-2008081300-dsw--0-ia5 08-Aug-2020 15:56                2149
ber01-VHDL13_DWLH_081333-2008081333-dsw--0-ia5     08-Aug-2020 13:33                1966
ber01-VHDL13_DWLH_081433-2008081433-dsw--0-ia5     08-Aug-2020 14:33                1966
ber01-VHDL13_DWLH_081533-2008081533-dsw--0-ia5     08-Aug-2020 15:33                2173
ber01-VHDL13_DWLH_081633-2008081633-dsw--0-ia5     08-Aug-2020 16:33                2158
ber01-VHDL13_DWLH_081733-2008081733-dsw--0-ia5     08-Aug-2020 17:33                2109
ber01-VHDL13_DWLH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2125
ber01-VHDL13_DWLH_081933-2008081933-dsw--0-ia5     08-Aug-2020 19:33                2153
ber01-VHDL13_DWLH_082033-2008082033-dsw--0-ia5     08-Aug-2020 20:33                2153
ber01-VHDL13_DWLH_090033-2008090033-dsw--0-ia5     09-Aug-2020 00:33                2139
ber01-VHDL13_DWLH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2184
ber01-VHDL13_DWLH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2185
ber01-VHDL13_DWLH_090533-2008090533-dsw--0-ia5     09-Aug-2020 05:33                2151
ber01-VHDL13_DWLH_090633-2008090633-dsw--0-ia5     09-Aug-2020 06:33                2151
ber01-VHDL13_DWLH_090733-2008090733-dsw--0-ia5     09-Aug-2020 07:33                2151
ber01-VHDL13_DWLH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2113
ber01-VHDL13_DWLI_070933-2008070933-dsw--0-ia5     07-Aug-2020 09:33                1940
ber01-VHDL13_DWLI_071033-2008071033-dsw--0-ia5     07-Aug-2020 10:33                1937
ber01-VHDL13_DWLI_071133-2008071133-dsw--0-ia5     07-Aug-2020 11:33                1937
ber01-VHDL13_DWLI_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                1882
ber01-VHDL13_DWLI_071333-2008071333-dsw--0-ia5     07-Aug-2020 13:33                1868
ber01-VHDL13_DWLI_071433-2008071433-dsw--0-ia5     07-Aug-2020 14:33                1868
ber01-VHDL13_DWLI_071533-2008071533-dsw--0-ia5     07-Aug-2020 15:33                1868
ber01-VHDL13_DWLI_071633-2008071633-dsw--0-ia5     07-Aug-2020 16:33                1868
ber01-VHDL13_DWLI_071733-2008071733-dsw--0-ia5     07-Aug-2020 17:33                1746
ber01-VHDL13_DWLI_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1681
ber01-VHDL13_DWLI_071933-2008071933-dsw--0-ia5     07-Aug-2020 19:33                1709
ber01-VHDL13_DWLI_072033-2008072033-dsw--0-ia5     07-Aug-2020 20:33                1709
ber01-VHDL13_DWLI_080033-2008080033-dsw--0-ia5     08-Aug-2020 00:33                1845
ber01-VHDL13_DWLI_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1836
ber01-VHDL13_DWLI_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1809
ber01-VHDL13_DWLI_080533-2008080533-dsw--0-ia5     08-Aug-2020 05:33                1837
ber01-VHDL13_DWLI_080633-2008080633-dsw--0-ia5     08-Aug-2020 06:33                1837
ber01-VHDL13_DWLI_080733-2008080733-dsw--0-ia5     08-Aug-2020 07:33                1837
ber01-VHDL13_DWLI_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1938
ber01-VHDL13_DWLI_080933-2008080933-dsw--0-ia5     08-Aug-2020 09:33                1966
ber01-VHDL13_DWLI_081033-2008081033-dsw--0-ia5     08-Aug-2020 10:33                1998
ber01-VHDL13_DWLI_081133-2008081133-dsw--0-ia5     08-Aug-2020 11:33                1998
ber01-VHDL13_DWLI_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                1907
ber01-VHDL13_DWLI_081300_COR-2008081300-dsw--0-ia5 08-Aug-2020 16:17                2251
ber01-VHDL13_DWLI_081333-2008081333-dsw--0-ia5     08-Aug-2020 13:33                2069
ber01-VHDL13_DWLI_081433-2008081433-dsw--0-ia5     08-Aug-2020 14:33                2069
ber01-VHDL13_DWLI_081533-2008081533-dsw--0-ia5     08-Aug-2020 15:33                2069
ber01-VHDL13_DWLI_081633-2008081633-dsw--0-ia5     08-Aug-2020 16:33                2275
ber01-VHDL13_DWLI_081733-2008081733-dsw--0-ia5     08-Aug-2020 17:33                2088
ber01-VHDL13_DWLI_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2103
ber01-VHDL13_DWLI_081933-2008081933-dsw--0-ia5     08-Aug-2020 19:33                2131
ber01-VHDL13_DWLI_082033-2008082033-dsw--0-ia5     08-Aug-2020 20:33                2131
ber01-VHDL13_DWLI_090033-2008090033-dsw--0-ia5     09-Aug-2020 00:33                2106
ber01-VHDL13_DWLI_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2108
ber01-VHDL13_DWLI_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2088
ber01-VHDL13_DWLI_090533-2008090533-dsw--0-ia5     09-Aug-2020 05:33                2041
ber01-VHDL13_DWLI_090633-2008090633-dsw--0-ia5     09-Aug-2020 06:33                2041
ber01-VHDL13_DWLI_090733-2008090733-dsw--0-ia5     09-Aug-2020 07:33                2041
ber01-VHDL13_DWLI_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2013
ber01-VHDL13_DWMG_070900-2008070900-dsw--0-ia5     07-Aug-2020 09:30                2136
ber01-VHDL13_DWMG_071000-2008071000-dsw--0-ia5     07-Aug-2020 10:30                2175
ber01-VHDL13_DWMG_071100-2008071100-dsw--0-ia5     07-Aug-2020 11:30                2175
ber01-VHDL13_DWMG_071200-2008071200-dsw--0-ia5     07-Aug-2020 12:30                2193
ber01-VHDL13_DWMG_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                2267
ber01-VHDL13_DWMG_071400-2008071400-dsw--0-ia5     07-Aug-2020 14:30                2228
ber01-VHDL13_DWMG_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2228
ber01-VHDL13_DWMG_071600-2008071600-dsw--0-ia5     07-Aug-2020 16:30                2228
ber01-VHDL13_DWMG_071700-2008071700-dsw--0-ia5     07-Aug-2020 17:30                2106
ber01-VHDL13_DWMG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2106
ber01-VHDL13_DWMG_071900-2008071900-dsw--0-ia5     07-Aug-2020 19:30                2126
ber01-VHDL13_DWMG_072000-2008072000-dsw--0-ia5     07-Aug-2020 20:30                2126
ber01-VHDL13_DWMG_072100-2008072100-dsw--0-ia5     07-Aug-2020 21:30                2149
ber01-VHDL13_DWMG_072200-2008072200-dsw--0-ia5     07-Aug-2020 22:30                2319
ber01-VHDL13_DWMG_072300-2008072300-dsw--0-ia5     07-Aug-2020 23:30                2319
ber01-VHDL13_DWMG_080000-2008080000-dsw--0-ia5     08-Aug-2020 00:30                2319
ber01-VHDL13_DWMG_080100-2008080100-dsw--0-ia5     08-Aug-2020 01:30                2319
ber01-VHDL13_DWMG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2201
ber01-VHDL13_DWMG_080300-2008080300-dsw--0-ia5     08-Aug-2020 03:30                2201
ber01-VHDL13_DWMG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2182
ber01-VHDL13_DWMG_080500-2008080500-dsw--0-ia5     08-Aug-2020 05:30                2182
ber01-VHDL13_DWMG_080600-2008080600-dsw--0-ia5     08-Aug-2020 06:30                2354
ber01-VHDL13_DWMG_080700-2008080700-dsw--0-ia5     08-Aug-2020 07:30                2354
ber01-VHDL13_DWMG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2348
ber01-VHDL13_DWMG_080900-2008080900-dsw--0-ia5     08-Aug-2020 09:30                2348
ber01-VHDL13_DWMG_081000-2008081000-dsw--0-ia5     08-Aug-2020 10:30                2348
ber01-VHDL13_DWMG_081100-2008081100-dsw--0-ia5     08-Aug-2020 11:30                2590
ber01-VHDL13_DWMG_081200-2008081200-dsw--0-ia5     08-Aug-2020 12:30                2590
ber01-VHDL13_DWMG_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                2590
ber01-VHDL13_DWMG_081400-2008081400-dsw--0-ia5     08-Aug-2020 14:30                2590
ber01-VHDL13_DWMG_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2590
ber01-VHDL13_DWMG_081600-2008081600-dsw--0-ia5     08-Aug-2020 16:30                2590
ber01-VHDL13_DWMG_081700-2008081700-dsw--0-ia5     08-Aug-2020 17:30                2440
ber01-VHDL13_DWMG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2377
ber01-VHDL13_DWMG_081900-2008081900-dsw--0-ia5     08-Aug-2020 19:30                2396
ber01-VHDL13_DWMG_082000-2008082000-dsw--0-ia5     08-Aug-2020 20:30                2382
ber01-VHDL13_DWMG_082100-2008082100-dsw--0-ia5     08-Aug-2020 21:30                2382
ber01-VHDL13_DWMG_082200-2008082200-dsw--0-ia5     08-Aug-2020 22:30                2711
ber01-VHDL13_DWMG_082300-2008082300-dsw--0-ia5     08-Aug-2020 23:30                2711
ber01-VHDL13_DWMG_090000-2008090000-dsw--0-ia5     09-Aug-2020 00:30                2711
ber01-VHDL13_DWMG_090100-2008090100-dsw--0-ia5     09-Aug-2020 01:30                2711
ber01-VHDL13_DWMG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2702
ber01-VHDL13_DWMG_090300-2008090300-dsw--0-ia5     09-Aug-2020 03:30                2702
ber01-VHDL13_DWMG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2689
ber01-VHDL13_DWMG_090500-2008090500-dsw--0-ia5     09-Aug-2020 05:30                2689
ber01-VHDL13_DWMG_090600-2008090600-dsw--0-ia5     09-Aug-2020 06:30                2792
ber01-VHDL13_DWMG_090700-2008090700-dsw--0-ia5     09-Aug-2020 07:30                2792
ber01-VHDL13_DWMG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2770
ber01-VHDL13_DWMO_070900-2008070900-dsw--0-ia5     07-Aug-2020 09:30                2252
ber01-VHDL13_DWMO_071000-2008071000-dsw--0-ia5     07-Aug-2020 10:30                2260
ber01-VHDL13_DWMO_071100-2008071100-dsw--0-ia5     07-Aug-2020 11:30                2260
ber01-VHDL13_DWMO_071200-2008071200-dsw--0-ia5     07-Aug-2020 12:30                2260
ber01-VHDL13_DWMO_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                2090
ber01-VHDL13_DWMO_071400-2008071400-dsw--0-ia5     07-Aug-2020 14:30                2055
ber01-VHDL13_DWMO_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2055
ber01-VHDL13_DWMO_071600-2008071600-dsw--0-ia5     07-Aug-2020 16:30                2055
ber01-VHDL13_DWMO_071700-2008071700-dsw--0-ia5     07-Aug-2020 17:30                2055
ber01-VHDL13_DWMO_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2055
ber01-VHDL13_DWMO_071900-2008071900-dsw--0-ia5     07-Aug-2020 19:30                1912
ber01-VHDL13_DWMO_072000-2008072000-dsw--0-ia5     07-Aug-2020 20:30                1912
ber01-VHDL13_DWMO_072100-2008072100-dsw--0-ia5     07-Aug-2020 21:30                1939
ber01-VHDL13_DWMO_072200-2008072200-dsw--0-ia5     07-Aug-2020 22:30                2182
ber01-VHDL13_DWMO_072300-2008072300-dsw--0-ia5     07-Aug-2020 23:30                2182
ber01-VHDL13_DWMO_080000-2008080000-dsw--0-ia5     08-Aug-2020 00:30                2182
ber01-VHDL13_DWMO_080100-2008080100-dsw--0-ia5     08-Aug-2020 01:30                2182
ber01-VHDL13_DWMO_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2177
ber01-VHDL13_DWMO_080300-2008080300-dsw--0-ia5     08-Aug-2020 03:30                2177
ber01-VHDL13_DWMO_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2177
ber01-VHDL13_DWMO_080500-2008080500-dsw--0-ia5     08-Aug-2020 05:30                2177
ber01-VHDL13_DWMO_080600-2008080600-dsw--0-ia5     08-Aug-2020 06:30                2177
ber01-VHDL13_DWMO_080700-2008080700-dsw--0-ia5     08-Aug-2020 07:30                2193
ber01-VHDL13_DWMO_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2210
ber01-VHDL13_DWMO_080900-2008080900-dsw--0-ia5     08-Aug-2020 09:30                2182
ber01-VHDL13_DWMO_081000-2008081000-dsw--0-ia5     08-Aug-2020 10:30                2182
ber01-VHDL13_DWMO_081100-2008081100-dsw--0-ia5     08-Aug-2020 11:30                2451
ber01-VHDL13_DWMO_081200-2008081200-dsw--0-ia5     08-Aug-2020 12:30                2451
ber01-VHDL13_DWMO_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                2451
ber01-VHDL13_DWMO_081400-2008081400-dsw--0-ia5     08-Aug-2020 14:30                2453
ber01-VHDL13_DWMO_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2453
ber01-VHDL13_DWMO_081600-2008081600-dsw--0-ia5     08-Aug-2020 16:30                2453
ber01-VHDL13_DWMO_081700-2008081700-dsw--0-ia5     08-Aug-2020 17:30                2348
ber01-VHDL13_DWMO_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2263
ber01-VHDL13_DWMO_081900-2008081900-dsw--0-ia5     08-Aug-2020 19:30                2283
ber01-VHDL13_DWMO_082000-2008082000-dsw--0-ia5     08-Aug-2020 20:30                2269
ber01-VHDL13_DWMO_082100-2008082100-dsw--0-ia5     08-Aug-2020 21:30                2269
ber01-VHDL13_DWMO_082200-2008082200-dsw--0-ia5     08-Aug-2020 22:30                2610
ber01-VHDL13_DWMO_082300-2008082300-dsw--0-ia5     08-Aug-2020 23:30                2610
ber01-VHDL13_DWMO_090000-2008090000-dsw--0-ia5     09-Aug-2020 00:30                2610
ber01-VHDL13_DWMO_090100-2008090100-dsw--0-ia5     09-Aug-2020 01:30                2610
ber01-VHDL13_DWMO_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2605
ber01-VHDL13_DWMO_090300-2008090300-dsw--0-ia5     09-Aug-2020 03:30                2605
ber01-VHDL13_DWMO_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2597
ber01-VHDL13_DWMO_090500-2008090500-dsw--0-ia5     09-Aug-2020 05:30                2597
ber01-VHDL13_DWMO_090600-2008090600-dsw--0-ia5     09-Aug-2020 06:30                2657
ber01-VHDL13_DWMO_090700-2008090700-dsw--0-ia5     09-Aug-2020 07:30                2657
ber01-VHDL13_DWMO_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2660
ber01-VHDL13_DWMP_070900-2008070900-dsw--0-ia5     07-Aug-2020 09:30                2158
ber01-VHDL13_DWMP_071000-2008071000-dsw--0-ia5     07-Aug-2020 10:30                2174
ber01-VHDL13_DWMP_071100-2008071100-dsw--0-ia5     07-Aug-2020 11:30                2174
ber01-VHDL13_DWMP_071200-2008071200-dsw--0-ia5     07-Aug-2020 12:30                2196
ber01-VHDL13_DWMP_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                2283
ber01-VHDL13_DWMP_071400-2008071400-dsw--0-ia5     07-Aug-2020 14:30                2258
ber01-VHDL13_DWMP_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2258
ber01-VHDL13_DWMP_071600-2008071600-dsw--0-ia5     07-Aug-2020 16:30                2258
ber01-VHDL13_DWMP_071700-2008071700-dsw--0-ia5     07-Aug-2020 17:30                2123
ber01-VHDL13_DWMP_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2123
ber01-VHDL13_DWMP_071900-2008071900-dsw--0-ia5     07-Aug-2020 19:30                2151
ber01-VHDL13_DWMP_072000-2008072000-dsw--0-ia5     07-Aug-2020 20:30                2151
ber01-VHDL13_DWMP_072100-2008072100-dsw--0-ia5     07-Aug-2020 21:30                2192
ber01-VHDL13_DWMP_072200-2008072200-dsw--0-ia5     07-Aug-2020 22:30                2331
ber01-VHDL13_DWMP_072300-2008072300-dsw--0-ia5     07-Aug-2020 23:30                2331
ber01-VHDL13_DWMP_080000-2008080000-dsw--0-ia5     08-Aug-2020 00:30                2331
ber01-VHDL13_DWMP_080100-2008080100-dsw--0-ia5     08-Aug-2020 01:30                2331
ber01-VHDL13_DWMP_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2179
ber01-VHDL13_DWMP_080300-2008080300-dsw--0-ia5     08-Aug-2020 03:30                2179
ber01-VHDL13_DWMP_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2179
ber01-VHDL13_DWMP_080500-2008080500-dsw--0-ia5     08-Aug-2020 05:30                2179
ber01-VHDL13_DWMP_080600-2008080600-dsw--0-ia5     08-Aug-2020 06:30                1879
ber01-VHDL13_DWMP_080700-2008080700-dsw--0-ia5     08-Aug-2020 07:30                1879
ber01-VHDL13_DWMP_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1879
ber01-VHDL13_DWMP_080900-2008080900-dsw--0-ia5     08-Aug-2020 09:30                1879
ber01-VHDL13_DWMP_081000-2008081000-dsw--0-ia5     08-Aug-2020 10:30                1879
ber01-VHDL13_DWMP_081100-2008081100-dsw--0-ia5     08-Aug-2020 11:30                2047
ber01-VHDL13_DWMP_081200-2008081200-dsw--0-ia5     08-Aug-2020 12:30                2047
ber01-VHDL13_DWMP_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                2047
ber01-VHDL13_DWMP_081400-2008081400-dsw--0-ia5     08-Aug-2020 14:30                2047
ber01-VHDL13_DWMP_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2047
ber01-VHDL13_DWMP_081600-2008081600-dsw--0-ia5     08-Aug-2020 16:30                2047
ber01-VHDL13_DWMP_081700-2008081700-dsw--0-ia5     08-Aug-2020 17:30                1917
ber01-VHDL13_DWMP_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                1877
ber01-VHDL13_DWMP_081900-2008081900-dsw--0-ia5     08-Aug-2020 19:30                1780
ber01-VHDL13_DWMP_082000-2008082000-dsw--0-ia5     08-Aug-2020 20:30                1699
ber01-VHDL13_DWMP_082100-2008082100-dsw--0-ia5     08-Aug-2020 21:30                1699
ber01-VHDL13_DWMP_082200-2008082200-dsw--0-ia5     08-Aug-2020 22:30                2133
ber01-VHDL13_DWMP_082300-2008082300-dsw--0-ia5     08-Aug-2020 23:30                2133
ber01-VHDL13_DWMP_090000-2008090000-dsw--0-ia5     09-Aug-2020 00:30                2133
ber01-VHDL13_DWMP_090100-2008090100-dsw--0-ia5     09-Aug-2020 01:30                2133
ber01-VHDL13_DWMP_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2148
ber01-VHDL13_DWMP_090300-2008090300-dsw--0-ia5     09-Aug-2020 03:30                2148
ber01-VHDL13_DWMP_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2140
ber01-VHDL13_DWMP_090500-2008090500-dsw--0-ia5     09-Aug-2020 05:30                2140
ber01-VHDL13_DWMP_090600-2008090600-dsw--0-ia5     09-Aug-2020 06:30                2427
ber01-VHDL13_DWMP_090700-2008090700-dsw--0-ia5     09-Aug-2020 07:30                2427
ber01-VHDL13_DWMP_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2413
ber01-VHDL13_DWOG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:00                3269
ber01-VHDL13_DWOG_071700-2008071700-dsw--0-ia5     07-Aug-2020 17:30                2697
ber01-VHDL13_DWOG_080100-2008080100-dsw--0-ia5     08-Aug-2020 01:45                3577
ber01-VHDL13_DWOG_080300-2008080300-dsw--0-ia5     08-Aug-2020 03:00                3576
ber01-VHDL13_DWOG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:15                3378
ber01-VHDL13_DWOG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:00                3285
ber01-VHDL13_DWOG_081700-2008081700-dsw--0-ia5     08-Aug-2020 17:30                2929
ber01-VHDL13_DWOG_090100-2008090100-dsw--0-ia5     09-Aug-2020 01:45                3015
ber01-VHDL13_DWOG_090300-2008090300-dsw--0-ia5     09-Aug-2020 03:00                3015
ber01-VHDL13_DWOG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:15                3933
ber01-VHDL13_DWOH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:28                2052
ber01-VHDL13_DWOH_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:28                2020
ber01-VHDL13_DWOH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:28                1947
ber01-VHDL13_DWOH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:28                2295
ber01-VHDL13_DWOH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:58                2237
ber01-VHDL13_DWOH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:28                2237
ber01-VHDL13_DWOH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:28                2207
ber01-VHDL13_DWOH_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:28                2653
ber01-VHDL13_DWOH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:28                2495
ber01-VHDL13_DWOH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:28                2927
ber01-VHDL13_DWOH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:58                2874
ber01-VHDL13_DWOH_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                2849
ber01-VHDL13_DWOH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:28                2880
ber01-VHDL13_DWOI_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:28                2165
ber01-VHDL13_DWOI_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:28                2173
ber01-VHDL13_DWOI_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:28                2100
ber01-VHDL13_DWOI_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:28                2414
ber01-VHDL13_DWOI_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:58                2349
ber01-VHDL13_DWOI_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:28                2355
ber01-VHDL13_DWOI_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:28                2309
ber01-VHDL13_DWOI_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:28                2749
ber01-VHDL13_DWOI_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:28                2623
ber01-VHDL13_DWOI_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:28                3019
ber01-VHDL13_DWOI_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:58                2962
ber01-VHDL13_DWOI_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                2957
ber01-VHDL13_DWOI_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:28                3010
ber01-VHDL13_DWON_071020-2008071020-dsw--0-ia5     07-Aug-2020 10:20                3557
ber01-VHDL13_DWON_071110-2008071110-dsw--0-ia5     07-Aug-2020 11:10                3557
ber01-VHDL13_DWON_071117-2008071117-dsw--0-ia5     07-Aug-2020 11:17                3557
ber01-VHDL13_DWON_071422-2008071422-dsw--0-ia5     07-Aug-2020 14:22                3365
ber01-VHDL13_DWON_071712-2008071712-dsw--0-ia5     07-Aug-2020 17:13                2691
ber01-VHDL13_DWON_071713-2008071713-dsw--0-ia5     07-Aug-2020 17:13                2691
ber01-VHDL13_DWON_071823-2008071823-dsw--0-ia5     07-Aug-2020 18:23                2690
ber01-VHDL13_DWON_071840-2008071840-dsw--0-ia5     07-Aug-2020 18:40                2838
ber01-VHDL13_DWON_072147-2008072147-dsw--0-ia5     07-Aug-2020 21:47                2866
ber01-VHDL13_DWON_072358-2008072358-dsw--0-ia5     07-Aug-2020 23:58                3481
ber01-VHDL13_DWON_080145-2008080145-dsw--0-ia5     08-Aug-2020 01:45                3459
ber01-VHDL13_DWON_080252-2008080252-dsw--0-ia5     08-Aug-2020 02:52                3459
ber01-VHDL13_DWON_080522-2008080522-dsw--0-ia5     08-Aug-2020 05:22                3488
ber01-VHDL13_DWON_080725-2008080725-dsw--0-ia5     08-Aug-2020 07:25                3481
ber01-VHDL13_DWON_081151-2008081151-dsw--0-ia5     08-Aug-2020 11:51                3450
ber01-VHDL13_DWON_081547-2008081547-dsw--0-ia5     08-Aug-2020 15:47                3148
ber01-VHDL13_DWON_081644-2008081644-dsw--0-ia5     08-Aug-2020 16:44                3162
ber01-VHDL13_DWON_081716-2008081716-dsw--0-ia5     08-Aug-2020 17:16                2801
ber01-VHDL13_DWON_090130-2008090130-dsw--0-ia5     09-Aug-2020 01:30                2745
ber01-VHDL13_DWON_090140-2008090140-dsw--0-ia5     09-Aug-2020 01:40                2801
ber01-VHDL13_DWON_090529-2008090529-dsw--0-ia5     09-Aug-2020 05:29                3311
ber01-VHDL13_DWON_090530-2008090530-dsw--0-ia5     09-Aug-2020 05:30                3309
ber01-VHDL13_DWON_090557-2008090557-dsw--0-ia5     09-Aug-2020 05:57                3756
ber01-VHDL13_DWON_090704-2008090704-dsw--0-ia5     09-Aug-2020 07:04                3804
ber01-VHDL13_DWPG_070930-2008070930-dsw--0-ia5     07-Aug-2020 09:30                2276
ber01-VHDL13_DWPG_071030-2008071030-dsw--0-ia5     07-Aug-2020 10:30                2276
ber01-VHDL13_DWPG_071130-2008071130-dsw--0-ia5     07-Aug-2020 11:30                2233
ber01-VHDL13_DWPG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2185
ber01-VHDL13_DWPG_071330-2008071330-dsw--0-ia5     07-Aug-2020 13:30                2184
ber01-VHDL13_DWPG_071430-2008071430-dsw--0-ia5     07-Aug-2020 14:30                2117
ber01-VHDL13_DWPG_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2088
ber01-VHDL13_DWPG_071630-2008071630-dsw--0-ia5     07-Aug-2020 16:30                2087
ber01-VHDL13_DWPG_071730-2008071730-dsw--0-ia5     07-Aug-2020 17:30                2087
ber01-VHDL13_DWPG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1922
ber01-VHDL13_DWPG_071930-2008071930-dsw--0-ia5     07-Aug-2020 19:30                1918
ber01-VHDL13_DWPG_072030-2008072030-dsw--0-ia5     07-Aug-2020 20:30                1918
ber01-VHDL13_DWPG_080030-2008080030-dsw--0-ia5     08-Aug-2020 00:30                1966
ber01-VHDL13_DWPG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2230
ber01-VHDL13_DWPG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2046
ber01-VHDL13_DWPG_080530-2008080530-dsw--0-ia5     08-Aug-2020 05:30                2044
ber01-VHDL13_DWPG_080630-2008080630-dsw--0-ia5     08-Aug-2020 06:30                2053
ber01-VHDL13_DWPG_080730-2008080730-dsw--0-ia5     08-Aug-2020 07:30                2166
ber01-VHDL13_DWPG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2168
ber01-VHDL13_DWPG_080930-2008080930-dsw--0-ia5     08-Aug-2020 09:30                2167
ber01-VHDL13_DWPG_081030-2008081030-dsw--0-ia5     08-Aug-2020 10:30                2167
ber01-VHDL13_DWPG_081130-2008081130-dsw--0-ia5     08-Aug-2020 11:30                2167
ber01-VHDL13_DWPG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2235
ber01-VHDL13_DWPG_081330-2008081330-dsw--0-ia5     08-Aug-2020 13:30                2234
ber01-VHDL13_DWPG_081430-2008081430-dsw--0-ia5     08-Aug-2020 14:30                2234
ber01-VHDL13_DWPG_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2126
ber01-VHDL13_DWPG_081630-2008081630-dsw--0-ia5     08-Aug-2020 16:30                2125
ber01-VHDL13_DWPG_081730-2008081730-dsw--0-ia5     08-Aug-2020 17:30                2125
ber01-VHDL13_DWPG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2162
ber01-VHDL13_DWPG_081930-2008081930-dsw--0-ia5     08-Aug-2020 19:30                2161
ber01-VHDL13_DWPG_082030-2008082030-dsw--0-ia5     08-Aug-2020 20:30                2161
ber01-VHDL13_DWPG_090030-2008090030-dsw--0-ia5     09-Aug-2020 00:30                2263
ber01-VHDL13_DWPG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2352
ber01-VHDL13_DWPG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2158
ber01-VHDL13_DWPG_090530-2008090530-dsw--0-ia5     09-Aug-2020 05:30                2156
ber01-VHDL13_DWPG_090630-2008090630-dsw--0-ia5     09-Aug-2020 06:30                2156
ber01-VHDL13_DWPG_090730-2008090730-dsw--0-ia5     09-Aug-2020 07:30                2156
ber01-VHDL13_DWPG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2138
ber01-VHDL13_DWPH_070930-2008070930-dsw--0-ia5     07-Aug-2020 09:30                2561
ber01-VHDL13_DWPH_071030-2008071030-dsw--0-ia5     07-Aug-2020 10:30                2561
ber01-VHDL13_DWPH_071130-2008071130-dsw--0-ia5     07-Aug-2020 11:30                2537
ber01-VHDL13_DWPH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2390
ber01-VHDL13_DWPH_071330-2008071330-dsw--0-ia5     07-Aug-2020 13:30                2390
ber01-VHDL13_DWPH_071430-2008071430-dsw--0-ia5     07-Aug-2020 14:30                2338
ber01-VHDL13_DWPH_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2368
ber01-VHDL13_DWPH_071630-2008071630-dsw--0-ia5     07-Aug-2020 16:30                2368
ber01-VHDL13_DWPH_071730-2008071730-dsw--0-ia5     07-Aug-2020 17:30                2368
ber01-VHDL13_DWPH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2072
ber01-VHDL13_DWPH_071930-2008071930-dsw--0-ia5     07-Aug-2020 19:30                2069
ber01-VHDL13_DWPH_072030-2008072030-dsw--0-ia5     07-Aug-2020 20:30                2069
ber01-VHDL13_DWPH_080030-2008080030-dsw--0-ia5     08-Aug-2020 00:30                2165
ber01-VHDL13_DWPH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2426
ber01-VHDL13_DWPH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2289
ber01-VHDL13_DWPH_080530-2008080530-dsw--0-ia5     08-Aug-2020 05:30                2289
ber01-VHDL13_DWPH_080630-2008080630-dsw--0-ia5     08-Aug-2020 06:30                2319
ber01-VHDL13_DWPH_080730-2008080730-dsw--0-ia5     08-Aug-2020 07:30                2417
ber01-VHDL13_DWPH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2384
ber01-VHDL13_DWPH_080930-2008080930-dsw--0-ia5     08-Aug-2020 09:30                2384
ber01-VHDL13_DWPH_081030-2008081030-dsw--0-ia5     08-Aug-2020 10:30                2384
ber01-VHDL13_DWPH_081130-2008081130-dsw--0-ia5     08-Aug-2020 11:30                2384
ber01-VHDL13_DWPH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2452
ber01-VHDL13_DWPH_081330-2008081330-dsw--0-ia5     08-Aug-2020 13:30                2452
ber01-VHDL13_DWPH_081430-2008081430-dsw--0-ia5     08-Aug-2020 14:30                2452
ber01-VHDL13_DWPH_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2450
ber01-VHDL13_DWPH_081630-2008081630-dsw--0-ia5     08-Aug-2020 16:30                2450
ber01-VHDL13_DWPH_081730-2008081730-dsw--0-ia5     08-Aug-2020 17:30                2450
ber01-VHDL13_DWPH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2276
ber01-VHDL13_DWPH_081930-2008081930-dsw--0-ia5     08-Aug-2020 19:30                2276
ber01-VHDL13_DWPH_082030-2008082030-dsw--0-ia5     08-Aug-2020 20:30                2276
ber01-VHDL13_DWPH_090030-2008090030-dsw--0-ia5     09-Aug-2020 00:30                2569
ber01-VHDL13_DWPH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2617
ber01-VHDL13_DWPH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2450
ber01-VHDL13_DWPH_090530-2008090530-dsw--0-ia5     09-Aug-2020 05:30                2450
ber01-VHDL13_DWPH_090630-2008090630-dsw--0-ia5     09-Aug-2020 06:30                2450
ber01-VHDL13_DWPH_090730-2008090730-dsw--0-ia5     09-Aug-2020 07:30                2527
ber01-VHDL13_DWPH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2536
ber01-VHDL13_DWSG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                1819
ber01-VHDL13_DWSG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1625
ber01-VHDL13_DWSG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2018
ber01-VHDL13_DWSG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2008
ber01-VHDL13_DWSG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1995
ber01-VHDL13_DWSG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2011
ber01-VHDL13_DWSG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                1955
ber01-VHDL13_DWSG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2272
ber01-VHDL13_DWSG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2219
ber01-VHDL13_DWSG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2217
ber01-VHDL13_DWSN_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                1532
ber01-VHDL13_DWSN_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1417
ber01-VHDL13_DWSN_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1656
ber01-VHDL13_DWSN_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1656
ber01-VHDL13_DWSN_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1519
ber01-VHDL13_DWSN_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                1678
ber01-VHDL13_DWSN_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                1626
ber01-VHDL13_DWSN_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                1994
ber01-VHDL13_DWSN_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                1926
ber01-VHDL13_DWSN_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                1922
ber01-VHDL13_DWSO_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                1735
ber01-VHDL13_DWSO_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1542
ber01-VHDL13_DWSO_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1848
ber01-VHDL13_DWSO_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1848
ber01-VHDL13_DWSO_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1811
ber01-VHDL13_DWSO_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                1813
ber01-VHDL13_DWSO_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                1784
ber01-VHDL13_DWSO_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2185
ber01-VHDL13_DWSO_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2115
ber01-VHDL13_DWSO_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2115
ber01-VHDL13_DWSP_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:30                1753
ber01-VHDL13_DWSP_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                1553
ber01-VHDL13_DWSP_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                1826
ber01-VHDL13_DWSP_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                1826
ber01-VHDL13_DWSP_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                1763
ber01-VHDL13_DWSP_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:30                1793
ber01-VHDL13_DWSP_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                1662
ber01-VHDL13_DWSP_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                1970
ber01-VHDL13_DWSP_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                1914
ber01-VHDL13_DWSP_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                1911
ber01-VHDL17_DWOG_071200-2008071200-dsw--0-ia5     07-Aug-2020 11:17                2548
ber01-VHDL17_DWOG_081200-2008081200-dsw--0-ia5     08-Aug-2020 11:40                2752
ber01-VHDL20_DWHG_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:45                2292
ber01-VHDL20_DWHG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2219
ber01-VHDL20_DWHG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2328
ber01-VHDL20_DWHG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2344
ber01-VHDL20_DWHG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2365
ber01-VHDL20_DWHG_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:45                2337
ber01-VHDL20_DWHG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2603
ber01-VHDL20_DWHG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3150
ber01-VHDL20_DWHG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                3128
ber01-VHDL20_DWHG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2904
ber01-VHDL20_DWHH_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:45                2216
ber01-VHDL20_DWHH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2181
ber01-VHDL20_DWHH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2330
ber01-VHDL20_DWHH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2321
ber01-VHDL20_DWHH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2353
ber01-VHDL20_DWHH_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:45                2315
ber01-VHDL20_DWHH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2331
ber01-VHDL20_DWHH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2771
ber01-VHDL20_DWHH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2771
ber01-VHDL20_DWHH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2493
gts01-VHDL12_DWON_071330-2008071230-afsv--83-ia5   07-Aug-2020 12:30                2974
gts01-VHDL12_DWON_071815-2008071745-afsv--14-ia5   07-Aug-2020 17:45                2188
gts01-VHDL12_DWON_080115-2008080145-afsv--56-ia5   08-Aug-2020 01:45                2976
gts01-VHDL12_DWON_080530-2008080530-afsv--65-ia5   08-Aug-2020 05:30                2985
gts01-VHDL12_DWON_080815-2008080815-afsv--41-ia5   08-Aug-2020 08:15                2978
gts01-VHDL12_DWON_081330-2008081230-afsv--82-ia5   08-Aug-2020 12:30                3031
gts01-VHDL12_DWON_081815-2008081745-afsv--31-ia5   08-Aug-2020 17:45                2345
gts01-VHDL12_DWON_090115-2008090145-afsv--57-ia5   09-Aug-2020 01:45                2359
gts01-VHDL12_DWON_090530-2008090530-afsv--76-ia5   09-Aug-2020 05:30                2887
gts01-VHDL12_DWON_090815-2008090815-afsv--71-ia5   09-Aug-2020 08:15                3232
pid-VHDL12_DWEH_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:28                1983
pid-VHDL12_DWEH_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:28                2497
pid-VHDL12_DWHG_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1835
pid-VHDL12_DWHG_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1850
pid-VHDL12_DWHG_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                2605
pid-VHDL12_DWHG_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                2582
pid-VHDL12_DWHH_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1809
pid-VHDL12_DWHH_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1800
pid-VHDL12_DWHH_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                2168
pid-VHDL12_DWHH_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                2168
pid-VHDL12_DWLG_071300-2008071300-dsw--0-ia5       07-Aug-2020 12:30                1608
pid-VHDL12_DWLG_071800-2008071800-dsw--0-ia5       07-Aug-2020 18:30                1404
pid-VHDL12_DWLG_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1580
pid-VHDL12_DWLG_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1562
pid-VHDL12_DWLG_080800-2008080800-dsw--0-ia5       08-Aug-2020 08:30                1700
pid-VHDL12_DWLG_081300-2008081300-dsw--0-ia5       08-Aug-2020 12:30                1662
pid-VHDL12_DWLG_081800-2008081800-dsw--0-ia5       08-Aug-2020 18:30                1832
pid-VHDL12_DWLG_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                1893
pid-VHDL12_DWLG_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                1865
pid-VHDL12_DWLG_090800-2008090800-dsw--0-ia5       09-Aug-2020 08:30                1807
pid-VHDL12_DWLH_071300-2008071300-dsw--0-ia5       07-Aug-2020 12:30                1588
pid-VHDL12_DWLH_071800-2008071800-dsw--0-ia5       07-Aug-2020 18:30                1388
pid-VHDL12_DWLH_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1523
pid-VHDL12_DWLH_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1507
pid-VHDL12_DWLH_080800-2008080800-dsw--0-ia5       08-Aug-2020 08:30                1624
pid-VHDL12_DWLH_081300-2008081300-dsw--0-ia5       08-Aug-2020 12:30                1590
pid-VHDL12_DWLH_081800-2008081800-dsw--0-ia5       08-Aug-2020 18:30                1867
pid-VHDL12_DWLH_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                1936
pid-VHDL12_DWLH_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                1937
pid-VHDL12_DWLH_090800-2008090800-dsw--0-ia5       09-Aug-2020 08:30                1865
pid-VHDL12_DWLI_071300-2008071300-dsw--0-ia5       07-Aug-2020 12:30                1599
pid-VHDL12_DWLI_071800-2008071800-dsw--0-ia5       07-Aug-2020 18:30                1395
pid-VHDL12_DWLI_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1565
pid-VHDL12_DWLI_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1547
pid-VHDL12_DWLI_080800-2008080800-dsw--0-ia5       08-Aug-2020 08:30                1676
pid-VHDL12_DWLI_081300-2008081300-dsw--0-ia5       08-Aug-2020 12:30                1645
pid-VHDL12_DWLI_081300_COR-2008081300-dsw--0-ia5   08-Aug-2020 16:16                1989
pid-VHDL12_DWLI_081800-2008081800-dsw--0-ia5       08-Aug-2020 18:30                1841
pid-VHDL12_DWLI_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                1855
pid-VHDL12_DWLI_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                1835
pid-VHDL12_DWLI_090800-2008090800-dsw--0-ia5       09-Aug-2020 08:30                1760
pid-VHDL12_DWMG_071300-2008071300-dsw--0-ia5       07-Aug-2020 12:30                1821
pid-VHDL12_DWMG_071800-2008071800-dsw--0-ia5       07-Aug-2020 18:30                1773
pid-VHDL12_DWMG_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1836
pid-VHDL12_DWMG_080400-2008080400-dsw--0-ia5       08-Aug-2020 04:30                1817
pid-VHDL12_DWMG_080800-2008080800-dsw--0-ia5       08-Aug-2020 08:30                1952
pid-VHDL12_DWMG_081300-2008081300-dsw--0-ia5       08-Aug-2020 12:30                2194
pid-VHDL12_DWMG_081800-2008081800-dsw--0-ia5       08-Aug-2020 18:30                1981
pid-VHDL12_DWMG_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                2157
pid-VHDL12_DWMG_090400-2008090400-dsw--0-ia5       09-Aug-2020 04:30                2144
pid-VHDL12_DWMG_090800-2008090800-dsw--0-ia5       09-Aug-2020 08:30                2264
pid-VHDL12_DWOG_080100-2008080100-dsw--0-ia5       08-Aug-2020 01:45                2983
pid-VHDL12_DWOG_080300-2008080300-dsw--0-ia5       08-Aug-2020 03:00                2982
pid-VHDL12_DWOG_090100-2008090100-dsw--0-ia5       09-Aug-2020 01:45                2503
pid-VHDL12_DWOG_090300-2008090300-dsw--0-ia5       09-Aug-2020 03:00                2503
pid-VHDL12_DWOH_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:28                1905
pid-VHDL12_DWOH_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:28                2479
pid-VHDL12_DWOI_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:28                2025
pid-VHDL12_DWOI_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:28                2571
pid-VHDL12_DWSG_080200-2008080200-dsw--0-ia5       08-Aug-2020 02:30                1668
pid-VHDL12_DWSG_090200-2008090200-dsw--0-ia5       09-Aug-2020 02:30                1820
swis2-VHDL20_DWEG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2262
swis2-VHDL20_DWEG_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:45                2227
swis2-VHDL20_DWEG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2160
swis2-VHDL20_DWEG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2455
swis2-VHDL20_DWEG_080400-2008080400-dsw--0-ia5     08-Aug-2020 05:15                2444
swis2-VHDL20_DWEG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2444
swis2-VHDL20_DWEG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2423
swis2-VHDL20_DWEG_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:45                2860
swis2-VHDL20_DWEG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2708
swis2-VHDL20_DWEG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3087
swis2-VHDL20_DWEG_090400-2008090400-dsw--0-ia5     09-Aug-2020 05:15                3081
swis2-VHDL20_DWEG_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                3056
swis2-VHDL20_DWEG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                3087
swis2-VHDL20_DWEH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2308
swis2-VHDL20_DWEH_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:45                2325
swis2-VHDL20_DWEH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2277
swis2-VHDL20_DWEH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2565
swis2-VHDL20_DWEH_080400-2008080400-dsw--0-ia5     08-Aug-2020 05:15                2517
swis2-VHDL20_DWEH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2517
swis2-VHDL20_DWEH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2493
swis2-VHDL20_DWEH_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:45                2941
swis2-VHDL20_DWEH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2803
swis2-VHDL20_DWEH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3138
swis2-VHDL20_DWEH_090400-2008090400-dsw--0-ia5     09-Aug-2020 05:15                3236
swis2-VHDL20_DWEH_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                3215
swis2-VHDL20_DWEH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                3286
swis2-VHDL20_DWEI_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2378
swis2-VHDL20_DWEI_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:45                2386
swis2-VHDL20_DWEI_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2313
swis2-VHDL20_DWEI_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2575
swis2-VHDL20_DWEI_080400-2008080400-dsw--0-ia5     08-Aug-2020 05:15                2562
swis2-VHDL20_DWEI_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2562
swis2-VHDL20_DWEI_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2522
swis2-VHDL20_DWEI_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:45                2962
swis2-VHDL20_DWEI_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2836
swis2-VHDL20_DWEI_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3180
swis2-VHDL20_DWEI_090400-2008090400-dsw--0-ia5     09-Aug-2020 05:15                3175
swis2-VHDL20_DWEI_090400_COR-2008090400-dsw--0-ia5 09-Aug-2020 07:46                3170
swis2-VHDL20_DWEI_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                3217
swis2-VHDL20_DWHG_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:45                2292
swis2-VHDL20_DWHG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2219
swis2-VHDL20_DWHG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2328
swis2-VHDL20_DWHG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2344
swis2-VHDL20_DWHG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2365
swis2-VHDL20_DWHG_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:45                2337
swis2-VHDL20_DWHG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2603
swis2-VHDL20_DWHG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3150
swis2-VHDL20_DWHG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                3128
swis2-VHDL20_DWHG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2904
swis2-VHDL20_DWHH_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:45                2216
swis2-VHDL20_DWHH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2181
swis2-VHDL20_DWHH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2330
swis2-VHDL20_DWHH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2321
swis2-VHDL20_DWHH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2353
swis2-VHDL20_DWHH_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:45                2315
swis2-VHDL20_DWHH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2331
swis2-VHDL20_DWHH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2771
swis2-VHDL20_DWHH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2771
swis2-VHDL20_DWHH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2493
swis2-VHDL20_DWLG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2144
swis2-VHDL20_DWLG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                1943
swis2-VHDL20_DWLG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2122
swis2-VHDL20_DWLG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2095
swis2-VHDL20_DWLG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2233
swis2-VHDL20_DWLG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2195
swis2-VHDL20_DWLG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2368
swis2-VHDL20_DWLG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2399
swis2-VHDL20_DWLG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2313
swis2-VHDL20_DWLG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2313
swis2-VHDL20_DWLH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2081
swis2-VHDL20_DWLH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                1884
swis2-VHDL20_DWLH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2043
swis2-VHDL20_DWLH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2018
swis2-VHDL20_DWLH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2135
swis2-VHDL20_DWLH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2101
swis2-VHDL20_DWLH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2378
swis2-VHDL20_DWLH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2437
swis2-VHDL20_DWLH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2376
swis2-VHDL20_DWLH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2366
swis2-VHDL20_DWLI_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2135
swis2-VHDL20_DWLI_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                1934
swis2-VHDL20_DWLI_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2089
swis2-VHDL20_DWLI_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2062
swis2-VHDL20_DWLI_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2191
swis2-VHDL20_DWLI_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2160
swis2-VHDL20_DWLI_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2356
swis2-VHDL20_DWLI_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2361
swis2-VHDL20_DWLI_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2266
swis2-VHDL20_DWLI_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2266
swis2-VHDL20_DWMG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                3017
swis2-VHDL20_DWMG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2930
swis2-VHDL20_DWMG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                3025
swis2-VHDL20_DWMG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                3006
swis2-VHDL20_DWMG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                3172
swis2-VHDL20_DWMG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                3414
swis2-VHDL20_DWMG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                3201
swis2-VHDL20_DWMG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3487
swis2-VHDL20_DWMG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                3512
swis2-VHDL20_DWMG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                3593
swis2-VHDL20_DWMO_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2836
swis2-VHDL20_DWMO_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2631
swis2-VHDL20_DWMO_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2752
swis2-VHDL20_DWMO_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2756
swis2-VHDL20_DWMO_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2758
swis2-VHDL20_DWMO_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                3027
swis2-VHDL20_DWMO_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2839
swis2-VHDL20_DWMO_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                3180
swis2-VHDL20_DWMO_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                3175
swis2-VHDL20_DWMO_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                3207
swis2-VHDL20_DWMP_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:45                2774
swis2-VHDL20_DWMP_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                2680
swis2-VHDL20_DWMP_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2756
swis2-VHDL20_DWMP_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2757
swis2-VHDL20_DWMP_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2457
swis2-VHDL20_DWMP_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:45                2625
swis2-VHDL20_DWMP_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2428
swis2-VHDL20_DWMP_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2725
swis2-VHDL20_DWMP_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2717
swis2-VHDL20_DWMP_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2990
swis2-VHDL20_DWPG_070930-2008070930-dsw--0-ia5     07-Aug-2020 09:30                2463
swis2-VHDL20_DWPG_071030-2008071030-dsw--0-ia5     07-Aug-2020 10:30                2463
swis2-VHDL20_DWPG_071130-2008071130-dsw--0-ia5     07-Aug-2020 11:30                2420
swis2-VHDL20_DWPG_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2371
swis2-VHDL20_DWPG_071330-2008071330-dsw--0-ia5     07-Aug-2020 13:30                2371
swis2-VHDL20_DWPG_071430-2008071430-dsw--0-ia5     07-Aug-2020 14:30                2304
swis2-VHDL20_DWPG_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2274
swis2-VHDL20_DWPG_071630-2008071630-dsw--0-ia5     07-Aug-2020 16:30                2274
swis2-VHDL20_DWPG_071730-2008071730-dsw--0-ia5     07-Aug-2020 17:30                2274
swis2-VHDL20_DWPG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2109
swis2-VHDL20_DWPG_071930-2008071930-dsw--0-ia5     07-Aug-2020 19:30                2105
swis2-VHDL20_DWPG_072030-2008072030-dsw--0-ia5     07-Aug-2020 20:30                2105
swis2-VHDL20_DWPG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2417
swis2-VHDL20_DWPG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2231
swis2-VHDL20_DWPG_080530-2008080530-dsw--0-ia5     08-Aug-2020 05:30                2231
swis2-VHDL20_DWPG_080630-2008080630-dsw--0-ia5     08-Aug-2020 06:30                2240
swis2-VHDL20_DWPG_080730-2008080730-dsw--0-ia5     08-Aug-2020 07:30                2353
swis2-VHDL20_DWPG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2355
swis2-VHDL20_DWPG_080930-2008080930-dsw--0-ia5     08-Aug-2020 09:30                2354
swis2-VHDL20_DWPG_081030-2008081030-dsw--0-ia5     08-Aug-2020 10:30                2354
swis2-VHDL20_DWPG_081130-2008081130-dsw--0-ia5     08-Aug-2020 11:30                2354
swis2-VHDL20_DWPG_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2421
swis2-VHDL20_DWPG_081330-2008081330-dsw--0-ia5     08-Aug-2020 13:30                2421
swis2-VHDL20_DWPG_081430-2008081430-dsw--0-ia5     08-Aug-2020 14:30                2421
swis2-VHDL20_DWPG_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2312
swis2-VHDL20_DWPG_081630-2008081630-dsw--0-ia5     08-Aug-2020 16:30                2312
swis2-VHDL20_DWPG_081730-2008081730-dsw--0-ia5     08-Aug-2020 17:30                2312
swis2-VHDL20_DWPG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2349
swis2-VHDL20_DWPG_081930-2008081930-dsw--0-ia5     08-Aug-2020 19:30                2348
swis2-VHDL20_DWPG_082030-2008082030-dsw--0-ia5     08-Aug-2020 20:30                2348
swis2-VHDL20_DWPG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2539
swis2-VHDL20_DWPG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2343
swis2-VHDL20_DWPG_090530-2008090530-dsw--0-ia5     09-Aug-2020 05:30                2343
swis2-VHDL20_DWPG_090630-2008090630-dsw--0-ia5     09-Aug-2020 06:30                2343
swis2-VHDL20_DWPG_090730-2008090730-dsw--0-ia5     09-Aug-2020 07:30                2343
swis2-VHDL20_DWPG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2325
swis2-VHDL20_DWPH_070930-2008070930-dsw--0-ia5     07-Aug-2020 09:30                2748
swis2-VHDL20_DWPH_071030-2008071030-dsw--0-ia5     07-Aug-2020 10:30                2748
swis2-VHDL20_DWPH_071130-2008071130-dsw--0-ia5     07-Aug-2020 11:30                2724
swis2-VHDL20_DWPH_071300-2008071300-dsw--0-ia5     07-Aug-2020 12:30                2577
swis2-VHDL20_DWPH_071330-2008071330-dsw--0-ia5     07-Aug-2020 13:30                2577
swis2-VHDL20_DWPH_071430-2008071430-dsw--0-ia5     07-Aug-2020 14:30                2525
swis2-VHDL20_DWPH_071500-2008071500-dsw--0-ia5     07-Aug-2020 15:30                2555
swis2-VHDL20_DWPH_071630-2008071630-dsw--0-ia5     07-Aug-2020 16:30                2555
swis2-VHDL20_DWPH_071730-2008071730-dsw--0-ia5     07-Aug-2020 17:30                2555
swis2-VHDL20_DWPH_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:30                2259
swis2-VHDL20_DWPH_071930-2008071930-dsw--0-ia5     07-Aug-2020 19:30                2256
swis2-VHDL20_DWPH_072030-2008072030-dsw--0-ia5     07-Aug-2020 20:30                2256
swis2-VHDL20_DWPH_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:30                2613
swis2-VHDL20_DWPH_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:30                2476
swis2-VHDL20_DWPH_080530-2008080530-dsw--0-ia5     08-Aug-2020 05:30                2476
swis2-VHDL20_DWPH_080630-2008080630-dsw--0-ia5     08-Aug-2020 06:30                2506
swis2-VHDL20_DWPH_080730-2008080730-dsw--0-ia5     08-Aug-2020 07:30                2604
swis2-VHDL20_DWPH_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:30                2571
swis2-VHDL20_DWPH_080930-2008080930-dsw--0-ia5     08-Aug-2020 09:30                2571
swis2-VHDL20_DWPH_081030-2008081030-dsw--0-ia5     08-Aug-2020 10:30                2571
swis2-VHDL20_DWPH_081130-2008081130-dsw--0-ia5     08-Aug-2020 11:30                2571
swis2-VHDL20_DWPH_081300-2008081300-dsw--0-ia5     08-Aug-2020 12:30                2639
swis2-VHDL20_DWPH_081330-2008081330-dsw--0-ia5     08-Aug-2020 13:30                2639
swis2-VHDL20_DWPH_081430-2008081430-dsw--0-ia5     08-Aug-2020 14:30                2639
swis2-VHDL20_DWPH_081500-2008081500-dsw--0-ia5     08-Aug-2020 15:30                2637
swis2-VHDL20_DWPH_081630-2008081630-dsw--0-ia5     08-Aug-2020 16:30                2637
swis2-VHDL20_DWPH_081730-2008081730-dsw--0-ia5     08-Aug-2020 17:30                2637
swis2-VHDL20_DWPH_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:30                2463
swis2-VHDL20_DWPH_081930-2008081930-dsw--0-ia5     08-Aug-2020 19:30                2463
swis2-VHDL20_DWPH_082030-2008082030-dsw--0-ia5     08-Aug-2020 20:30                2463
swis2-VHDL20_DWPH_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:30                2804
swis2-VHDL20_DWPH_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:30                2637
swis2-VHDL20_DWPH_090530-2008090530-dsw--0-ia5     09-Aug-2020 05:30                2637
swis2-VHDL20_DWPH_090630-2008090630-dsw--0-ia5     09-Aug-2020 06:30                2637
swis2-VHDL20_DWPH_090730-2008090730-dsw--0-ia5     09-Aug-2020 07:30                2714
swis2-VHDL20_DWPH_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:30                2723
swis2-VHDL20_DWSG_071300-2008071300-dsw--0-ia5     07-Aug-2020 13:45                2051
swis2-VHDL20_DWSG_071800-2008071800-dsw--0-ia5     07-Aug-2020 18:45                1857
swis2-VHDL20_DWSG_080200-2008080200-dsw--0-ia5     08-Aug-2020 02:45                2252
swis2-VHDL20_DWSG_080400-2008080400-dsw--0-ia5     08-Aug-2020 04:45                2239
swis2-VHDL20_DWSG_080800-2008080800-dsw--0-ia5     08-Aug-2020 08:45                2225
swis2-VHDL20_DWSG_081300-2008081300-dsw--0-ia5     08-Aug-2020 13:45                2243
swis2-VHDL20_DWSG_081800-2008081800-dsw--0-ia5     08-Aug-2020 18:45                2187
swis2-VHDL20_DWSG_090200-2008090200-dsw--0-ia5     09-Aug-2020 02:45                2506
swis2-VHDL20_DWSG_090400-2008090400-dsw--0-ia5     09-Aug-2020 04:45                2450
swis2-VHDL20_DWSG_090800-2008090800-dsw--0-ia5     09-Aug-2020 08:45                2447
wst04-VHDL20_DWEG_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              250101
wst04-VHDL20_DWEG_071500-2008071500-omedes--0.pdf  07-Aug-2020 15:45              249553
wst04-VHDL20_DWEG_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              249446
wst04-VHDL20_DWEG_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              249468
wst04-VHDL20_DWEG_080400-2008080400-omedes--0.pdf  08-Aug-2020 05:15              249772
wst04-VHDL20_DWEG_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              254173
wst04-VHDL20_DWEG_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              254009
wst04-VHDL20_DWEG_081500-2008081500-omedes--0.pdf  08-Aug-2020 15:45              255089
wst04-VHDL20_DWEG_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              254891
wst04-VHDL20_DWEG_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              255100
wst04-VHDL20_DWEG_090400-2008090400-omedes--0.pdf  09-Aug-2020 05:15              255503
wst04-VHDL20_DWEG_090400_COR-2008090400-omedes-..> 09-Aug-2020 07:46              255487
wst04-VHDL20_DWEG_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              252670
wst04-VHDL20_DWEH_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              248950
wst04-VHDL20_DWEH_071500-2008071500-omedes--0.pdf  07-Aug-2020 15:45              248342
wst04-VHDL20_DWEH_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              248265
wst04-VHDL20_DWEH_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              248429
wst04-VHDL20_DWEH_080400-2008080400-omedes--0.pdf  08-Aug-2020 05:15              248225
wst04-VHDL20_DWEH_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              249414
wst04-VHDL20_DWEH_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              249200
wst04-VHDL20_DWEH_081500-2008081500-omedes--0.pdf  08-Aug-2020 15:45              250340
wst04-VHDL20_DWEH_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              250103
wst04-VHDL20_DWEH_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              250869
wst04-VHDL20_DWEH_090400-2008090400-omedes--0.pdf  09-Aug-2020 05:15              250761
wst04-VHDL20_DWEH_090400_COR-2008090400-omedes-..> 09-Aug-2020 07:46              250735
wst04-VHDL20_DWEH_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              248414
wst04-VHDL20_DWEI_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              346465
wst04-VHDL20_DWEI_071500-2008071500-omedes--0.pdf  07-Aug-2020 15:45              345825
wst04-VHDL20_DWEI_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              345754
wst04-VHDL20_DWEI_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              345898
wst04-VHDL20_DWEI_080400-2008080400-omedes--0.pdf  08-Aug-2020 05:15              345668
wst04-VHDL20_DWEI_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              351765
wst04-VHDL20_DWEI_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              351596
wst04-VHDL20_DWEI_081500-2008081500-omedes--0.pdf  08-Aug-2020 15:45              352717
wst04-VHDL20_DWEI_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              352509
wst04-VHDL20_DWEI_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              353292
wst04-VHDL20_DWEI_090400-2008090400-omedes--0.pdf  09-Aug-2020 05:15              352982
wst04-VHDL20_DWEI_090400_COR-2008090400-omedes-..> 09-Aug-2020 07:46              353063
wst04-VHDL20_DWEI_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              351307
wst04-VHDL20_DWHG_071300-2008071300-oflxs888--0..> 07-Aug-2020 13:45              344291
wst04-VHDL20_DWHG_071800-2008071800-oflxs888--0..> 07-Aug-2020 18:45              344351
wst04-VHDL20_DWHG_080200-2008080200-oflxs888--0..> 08-Aug-2020 02:45              344361
wst04-VHDL20_DWHG_080400-2008080400-oflxs888--0..> 08-Aug-2020 04:45              344327
wst04-VHDL20_DWHG_080800-2008080800-oflxs888--0..> 08-Aug-2020 08:45              350286
wst04-VHDL20_DWHG_081300-2008081300-oflxs888--0..> 08-Aug-2020 13:45              349716
wst04-VHDL20_DWHG_081800-2008081800-oflxs888--0..> 08-Aug-2020 18:45              350185
wst04-VHDL20_DWHG_090200-2008090200-oflxs888--0..> 09-Aug-2020 02:45              350981
wst04-VHDL20_DWHG_090400-2008090400-oflxs888--0..> 09-Aug-2020 04:45              350928
wst04-VHDL20_DWHG_090800-2008090800-oflxs888--0..> 09-Aug-2020 08:45              358472
wst04-VHDL20_DWHH_071300-2008071300-oflxs888--0..> 07-Aug-2020 13:45              329453
wst04-VHDL20_DWHH_071800-2008071800-oflxs888--0..> 07-Aug-2020 18:45              329542
wst04-VHDL20_DWHH_080200-2008080200-oflxs888--0..> 08-Aug-2020 02:45              329477
wst04-VHDL20_DWHH_080400-2008080400-oflxs888--0..> 08-Aug-2020 04:45              329495
wst04-VHDL20_DWHH_080800-2008080800-oflxs888--0..> 08-Aug-2020 08:45              328654
wst04-VHDL20_DWHH_081300-2008081300-oflxs888--0..> 08-Aug-2020 13:45              328643
wst04-VHDL20_DWHH_081800-2008081800-oflxs888--0..> 08-Aug-2020 18:45              328564
wst04-VHDL20_DWHH_090200-2008090200-oflxs888--0..> 09-Aug-2020 02:45              329284
wst04-VHDL20_DWHH_090400-2008090400-oflxs888--0..> 09-Aug-2020 04:45              329334
wst04-VHDL20_DWHH_090800-2008090800-oflxs888--0..> 09-Aug-2020 08:45              335381
wst04-VHDL20_DWLG_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:40              253262
wst04-VHDL20_DWLG_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:40              253148
wst04-VHDL20_DWLG_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:40              253678
wst04-VHDL20_DWLG_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:40              253314
wst04-VHDL20_DWLG_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:40              254217
wst04-VHDL20_DWLG_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:40              254507
wst04-VHDL20_DWLG_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:40              254774
wst04-VHDL20_DWLG_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:40              254593
wst04-VHDL20_DWLG_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:40              254665
wst04-VHDL20_DWLG_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:40              254519
wst04-VHDL20_DWLH_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:40              248782
wst04-VHDL20_DWLH_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:40              248695
wst04-VHDL20_DWLH_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:40              249018
wst04-VHDL20_DWLH_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:40              248748
wst04-VHDL20_DWLH_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:40              253661
wst04-VHDL20_DWLH_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:40              253970
wst04-VHDL20_DWLH_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:40              254145
wst04-VHDL20_DWLH_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:40              254096
wst04-VHDL20_DWLH_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:40              254131
wst04-VHDL20_DWLH_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:40              251916
wst04-VHDL20_DWLI_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:40              249037
wst04-VHDL20_DWLI_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:40              248925
wst04-VHDL20_DWLI_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:40              249194
wst04-VHDL20_DWLI_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:40              248994
wst04-VHDL20_DWLI_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:40              249268
wst04-VHDL20_DWLI_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:40              249564
wst04-VHDL20_DWLI_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:40              249721
wst04-VHDL20_DWLI_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:40              249564
wst04-VHDL20_DWLI_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:40              249601
wst04-VHDL20_DWLI_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:40              255075
wst04-VHDL20_DWMG_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              256837
wst04-VHDL20_DWMG_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              256764
wst04-VHDL20_DWMG_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              258456
wst04-VHDL20_DWMG_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:45              257305
wst04-VHDL20_DWMG_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              261317
wst04-VHDL20_DWMG_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              262582
wst04-VHDL20_DWMG_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              262704
wst04-VHDL20_DWMG_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              263976
wst04-VHDL20_DWMG_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:45              263434
wst04-VHDL20_DWMG_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              268198
wst04-VHDL20_DWMO_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              254903
wst04-VHDL20_DWMO_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              254643
wst04-VHDL20_DWMO_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              254334
wst04-VHDL20_DWMO_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:45              254804
wst04-VHDL20_DWMO_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              257086
wst04-VHDL20_DWMO_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              257713
wst04-VHDL20_DWMO_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              257660
wst04-VHDL20_DWMO_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              258479
wst04-VHDL20_DWMO_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:45              258944
wst04-VHDL20_DWMO_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              258813
wst04-VHDL20_DWMP_071300-2008071300-omedes--0.pdf  07-Aug-2020 12:45              256042
wst04-VHDL20_DWMP_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              255792
wst04-VHDL20_DWMP_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              256263
wst04-VHDL20_DWMP_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:45              256363
wst04-VHDL20_DWMP_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              260078
wst04-VHDL20_DWMP_081300-2008081300-omedes--0.pdf  08-Aug-2020 12:45              260579
wst04-VHDL20_DWMP_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              260603
wst04-VHDL20_DWMP_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              261217
wst04-VHDL20_DWMP_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:45              261303
wst04-VHDL20_DWMP_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              266332
wst04-VHDL20_DWPG_070930-2008070930-oflxs892--0..> 07-Aug-2020 09:30              339815
wst04-VHDL20_DWPG_071030-2008071030-oflxs892--0..> 07-Aug-2020 10:30              339815
wst04-VHDL20_DWPG_071130-2008071130-oflxs892--0..> 07-Aug-2020 11:30              339766
wst04-VHDL20_DWPG_071300-2008071300-oflxs892--0..> 07-Aug-2020 12:30              339791
wst04-VHDL20_DWPG_071330-2008071330-oflxs892--0..> 07-Aug-2020 13:30              339767
wst04-VHDL20_DWPG_071430-2008071430-oflxs892--0..> 07-Aug-2020 14:30              339750
wst04-VHDL20_DWPG_071500-2008071500-oflxs892--0..> 07-Aug-2020 15:30              339749
wst04-VHDL20_DWPG_071630-2008071630-oflxs892--0..> 07-Aug-2020 16:30              339748
wst04-VHDL20_DWPG_071730-2008071730-oflxs892--0..> 07-Aug-2020 17:30              340070
wst04-VHDL20_DWPG_071800-2008071800-oflxs892--0..> 07-Aug-2020 18:30              339626
wst04-VHDL20_DWPG_071930-2008071930-oflxs892--0..> 07-Aug-2020 19:30              339600
wst04-VHDL20_DWPG_072030-2008072030-oflxs892--0..> 07-Aug-2020 20:30              339600
wst04-VHDL20_DWPG_080200-2008080200-oflxs892--0..> 08-Aug-2020 02:30              340881
wst04-VHDL20_DWPG_080400-2008080400-oflxs892--0..> 08-Aug-2020 04:30              340153
wst04-VHDL20_DWPG_080530-2008080530-oflxs892--0..> 08-Aug-2020 05:30              340151
wst04-VHDL20_DWPG_080630-2008080630-oflxs892--0..> 08-Aug-2020 06:30              340156
wst04-VHDL20_DWPG_080730-2008080730-oflxs892--0..> 08-Aug-2020 07:30              340342
wst04-VHDL20_DWPG_080800-2008080800-oflxs892--0..> 08-Aug-2020 08:30              388773
wst04-VHDL20_DWPG_080930-2008080930-oflxs892--0..> 08-Aug-2020 09:30              344166
wst04-VHDL20_DWPG_081030-2008081030-oflxs892--0..> 08-Aug-2020 10:30              344166
wst04-VHDL20_DWPG_081130-2008081130-oflxs892--0..> 08-Aug-2020 11:30              344166
wst04-VHDL20_DWPG_081300-2008081300-oflxs892--0..> 08-Aug-2020 12:30              344230
wst04-VHDL20_DWPG_081330-2008081330-oflxs892--0..> 08-Aug-2020 13:30              344218
wst04-VHDL20_DWPG_081430-2008081430-oflxs892--0..> 08-Aug-2020 14:30              344218
wst04-VHDL20_DWPG_081500-2008081500-oflxs892--0..> 08-Aug-2020 15:30              344208
wst04-VHDL20_DWPG_081630-2008081630-oflxs892--0..> 08-Aug-2020 16:30              344165
wst04-VHDL20_DWPG_081730-2008081730-oflxs892--0..> 08-Aug-2020 17:30              344165
wst04-VHDL20_DWPG_081800-2008081800-oflxs892--0..> 08-Aug-2020 18:30              344747
wst04-VHDL20_DWPG_081930-2008081930-oflxs892--0..> 08-Aug-2020 19:30              344720
wst04-VHDL20_DWPG_082030-2008082030-oflxs892--0..> 08-Aug-2020 20:30              344720
wst04-VHDL20_DWPG_090200-2008090200-oflxs892--0..> 09-Aug-2020 02:30              345345
wst04-VHDL20_DWPG_090400-2008090400-oflxs892--0..> 09-Aug-2020 04:30              345388
wst04-VHDL20_DWPG_090530-2008090530-oflxs892--0..> 09-Aug-2020 05:30              345356
wst04-VHDL20_DWPG_090630-2008090630-oflxs892--0..> 09-Aug-2020 06:30              345356
wst04-VHDL20_DWPG_090730-2008090730-oflxs892--0..> 09-Aug-2020 07:30              345356
wst04-VHDL20_DWPG_090800-2008090800-oflxs892--0..> 09-Aug-2020 08:30              397682
wst04-VHDL20_DWPH_070930-2008070930-oflxs892--0..> 07-Aug-2020 09:30              250216
wst04-VHDL20_DWPH_071030-2008071030-oflxs892--0..> 07-Aug-2020 10:30              250216
wst04-VHDL20_DWPH_071130-2008071130-oflxs892--0..> 07-Aug-2020 11:30              249798
wst04-VHDL20_DWPH_071300-2008071300-oflxs892--0..> 07-Aug-2020 12:30              249733
wst04-VHDL20_DWPH_071330-2008071330-oflxs892--0..> 07-Aug-2020 13:30              249695
wst04-VHDL20_DWPH_071430-2008071430-oflxs892--0..> 07-Aug-2020 14:30              249700
wst04-VHDL20_DWPH_071500-2008071500-oflxs892--0..> 07-Aug-2020 15:30              249682
wst04-VHDL20_DWPH_071630-2008071630-oflxs892--0..> 07-Aug-2020 16:30              249670
wst04-VHDL20_DWPH_071730-2008071730-oflxs892--0..> 07-Aug-2020 17:30              250044
wst04-VHDL20_DWPH_071800-2008071800-oflxs892--0..> 07-Aug-2020 18:30              294097
wst04-VHDL20_DWPH_071930-2008071930-oflxs892--0..> 07-Aug-2020 19:30              249467
wst04-VHDL20_DWPH_072030-2008072030-oflxs892--0..> 07-Aug-2020 20:30              249467
wst04-VHDL20_DWPH_080200-2008080200-oflxs892--0..> 08-Aug-2020 02:30              250785
wst04-VHDL20_DWPH_080400-2008080400-oflxs892--0..> 08-Aug-2020 04:30              250184
wst04-VHDL20_DWPH_080530-2008080530-oflxs892--0..> 08-Aug-2020 05:30              250105
wst04-VHDL20_DWPH_080630-2008080630-oflxs892--0..> 08-Aug-2020 06:30              250095
wst04-VHDL20_DWPH_080730-2008080730-oflxs892--0..> 08-Aug-2020 07:30              250334
wst04-VHDL20_DWPH_080800-2008080800-oflxs892--0..> 08-Aug-2020 08:30              296411
wst04-VHDL20_DWPH_080930-2008080930-oflxs892--0..> 08-Aug-2020 09:30              251789
wst04-VHDL20_DWPH_081030-2008081030-oflxs892--0..> 08-Aug-2020 10:30              251789
wst04-VHDL20_DWPH_081130-2008081130-oflxs892--0..> 08-Aug-2020 11:30              251785
wst04-VHDL20_DWPH_081300-2008081300-oflxs892--0..> 08-Aug-2020 12:30              251869
wst04-VHDL20_DWPH_081330-2008081330-oflxs892--0..> 08-Aug-2020 13:30              251834
wst04-VHDL20_DWPH_081430-2008081430-oflxs892--0..> 08-Aug-2020 14:30              251834
wst04-VHDL20_DWPH_081500-2008081500-oflxs892--0..> 08-Aug-2020 15:30              251906
wst04-VHDL20_DWPH_081630-2008081630-oflxs892--0..> 08-Aug-2020 16:30              251883
wst04-VHDL20_DWPH_081730-2008081730-oflxs892--0..> 08-Aug-2020 17:30              251883
wst04-VHDL20_DWPH_081800-2008081800-oflxs892--0..> 08-Aug-2020 18:30              296443
wst04-VHDL20_DWPH_081930-2008081930-oflxs892--0..> 08-Aug-2020 19:30              251844
wst04-VHDL20_DWPH_082030-2008082030-oflxs892--0..> 08-Aug-2020 20:30              251844
wst04-VHDL20_DWPH_090200-2008090200-oflxs892--0..> 09-Aug-2020 02:30              252627
wst04-VHDL20_DWPH_090400-2008090400-oflxs892--0..> 09-Aug-2020 04:30              252502
wst04-VHDL20_DWPH_090530-2008090530-oflxs892--0..> 09-Aug-2020 05:30              252013
wst04-VHDL20_DWPH_090630-2008090630-oflxs892--0..> 09-Aug-2020 06:30              252013
wst04-VHDL20_DWPH_090730-2008090730-oflxs892--0..> 09-Aug-2020 07:30              252075
wst04-VHDL20_DWPH_090800-2008090800-oflxs892--0..> 09-Aug-2020 08:30              304412
wst04-VHDL20_DWSG_071300-2008071300-omedes--0.pdf  07-Aug-2020 13:45              253556
wst04-VHDL20_DWSG_071800-2008071800-omedes--0.pdf  07-Aug-2020 18:45              253317
wst04-VHDL20_DWSG_080200-2008080200-omedes--0.pdf  08-Aug-2020 02:45              255127
wst04-VHDL20_DWSG_080400-2008080400-omedes--0.pdf  08-Aug-2020 04:45              255140
wst04-VHDL20_DWSG_080800-2008080800-omedes--0.pdf  08-Aug-2020 08:45              259892
wst04-VHDL20_DWSG_081300-2008081300-omedes--0.pdf  08-Aug-2020 13:45              260075
wst04-VHDL20_DWSG_081800-2008081800-omedes--0.pdf  08-Aug-2020 18:45              259427
wst04-VHDL20_DWSG_090200-2008090200-omedes--0.pdf  09-Aug-2020 02:45              260473
wst04-VHDL20_DWSG_090400-2008090400-omedes--0.pdf  09-Aug-2020 04:45              259459
wst04-VHDL20_DWSG_090800-2008090800-omedes--0.pdf  09-Aug-2020 08:45              255696