Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_200600                                 20-Oct-2019 08:16                3777
FPDL13_DWMZ_210600                                 21-Oct-2019 08:05                3422
SXDL31_DWAV_200800                                 20-Oct-2019 07:15                9775
SXDL31_DWAV_201800                                 20-Oct-2019 16:49               10852
SXDL31_DWAV_210800                                 21-Oct-2019 06:50               13494
SXDL31_DWAV_211800                                 21-Oct-2019 16:33                9884
SXDL33_DWAV_200000                                 20-Oct-2019 09:35               14442
SXDL33_DWAV_210000                                 21-Oct-2019 09:08                7640
ber01-FWDL39_DWMS_201230-1910201230-dsw--0-ia5     20-Oct-2019 12:01                1122
ber01-FWDL39_DWMS_211230-1910211230-dsw--0-ia5     21-Oct-2019 12:51                1158
ber01-VHDL13_DWEH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:28                1781
ber01-VHDL13_DWEH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:28                2006
ber01-VHDL13_DWEH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:58                1956
ber01-VHDL13_DWEH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:28                2017
ber01-VHDL13_DWEH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:28                1996
ber01-VHDL13_DWEH_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:28                1976
ber01-VHDL13_DWEH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:28                1920
ber01-VHDL13_DWEH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:28                2118
ber01-VHDL13_DWEH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:58                2161
ber01-VHDL13_DWEH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:28                2011
ber01-VHDL13_DWEH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:28                1975
ber01-VHDL13_DWEH_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:28                1952
ber01-VHDL13_DWHG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1622
ber01-VHDL13_DWHG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                1832
ber01-VHDL13_DWHG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1841
ber01-VHDL13_DWHG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2496
ber01-VHDL13_DWHG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2492
ber01-VHDL13_DWHG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                2369
ber01-VHDL13_DWHG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2335
ber01-VHDL13_DWHG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2168
ber01-VHDL13_DWHG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2214
ber01-VHDL13_DWHG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2170
ber01-VHDL13_DWHH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1822
ber01-VHDL13_DWHH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                1690
ber01-VHDL13_DWHH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1692
ber01-VHDL13_DWHH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2308
ber01-VHDL13_DWHH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2287
ber01-VHDL13_DWHH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                2151
ber01-VHDL13_DWHH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2110
ber01-VHDL13_DWHH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2109
ber01-VHDL13_DWHH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2105
ber01-VHDL13_DWHH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2315
ber01-VHDL13_DWLG_191733-1910191733-dsw--0-ia5     19-Oct-2019 17:33                1671
ber01-VHDL13_DWLG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1643
ber01-VHDL13_DWLG_191933-1910191933-dsw--0-ia5     19-Oct-2019 19:33                1671
ber01-VHDL13_DWLG_192033-1910192033-dsw--0-ia5     19-Oct-2019 20:33                1671
ber01-VHDL13_DWLG_200033-1910200033-dsw--0-ia5     20-Oct-2019 00:33                1835
ber01-VHDL13_DWLG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                1855
ber01-VHDL13_DWLG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1868
ber01-VHDL13_DWLG_200533-1910200533-dsw--0-ia5     20-Oct-2019 05:33                1896
ber01-VHDL13_DWLG_200633-1910200633-dsw--0-ia5     20-Oct-2019 06:33                1896
ber01-VHDL13_DWLG_200733-1910200733-dsw--0-ia5     20-Oct-2019 07:33                1896
ber01-VHDL13_DWLG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                1862
ber01-VHDL13_DWLG_200933-1910200933-dsw--0-ia5     20-Oct-2019 09:33                1823
ber01-VHDL13_DWLG_201033-1910201033-dsw--0-ia5     20-Oct-2019 10:33                1823
ber01-VHDL13_DWLG_201133-1910201133-dsw--0-ia5     20-Oct-2019 11:33                1823
ber01-VHDL13_DWLG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                1809
ber01-VHDL13_DWLG_201333-1910201333-dsw--0-ia5     20-Oct-2019 13:33                1837
ber01-VHDL13_DWLG_201433-1910201433-dsw--0-ia5     20-Oct-2019 14:33                1873
ber01-VHDL13_DWLG_201533-1910201533-dsw--0-ia5     20-Oct-2019 15:33                1873
ber01-VHDL13_DWLG_201633-1910201633-dsw--0-ia5     20-Oct-2019 16:33                1847
ber01-VHDL13_DWLG_201733-1910201733-dsw--0-ia5     20-Oct-2019 17:33                1592
ber01-VHDL13_DWLG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1564
ber01-VHDL13_DWLG_201933-1910201933-dsw--0-ia5     20-Oct-2019 19:33                1592
ber01-VHDL13_DWLG_202033-1910202033-dsw--0-ia5     20-Oct-2019 20:33                1592
ber01-VHDL13_DWLG_210033-1910210033-dsw--0-ia5     21-Oct-2019 00:33                1901
ber01-VHDL13_DWLG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                1873
ber01-VHDL13_DWLG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                1908
ber01-VHDL13_DWLG_210533-1910210533-dsw--0-ia5     21-Oct-2019 05:33                1940
ber01-VHDL13_DWLG_210633-1910210633-dsw--0-ia5     21-Oct-2019 06:33                1972
ber01-VHDL13_DWLG_210733-1910210733-dsw--0-ia5     21-Oct-2019 07:33                2028
ber01-VHDL13_DWLG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1997
ber01-VHDL13_DWLG_210933-1910210933-dsw--0-ia5     21-Oct-2019 09:33                2028
ber01-VHDL13_DWLG_211033-1910211033-dsw--0-ia5     21-Oct-2019 10:33                2028
ber01-VHDL13_DWLG_211133-1910211133-dsw--0-ia5     21-Oct-2019 11:33                2023
ber01-VHDL13_DWLG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                1987
ber01-VHDL13_DWLG_211333-1910211333-dsw--0-ia5     21-Oct-2019 13:33                1936
ber01-VHDL13_DWLG_211433-1910211433-dsw--0-ia5     21-Oct-2019 14:33                1936
ber01-VHDL13_DWLG_211533-1910211533-dsw--0-ia5     21-Oct-2019 15:33                1936
ber01-VHDL13_DWLG_211633-1910211633-dsw--0-ia5     21-Oct-2019 16:33                1936
ber01-VHDL13_DWLH_191733-1910191733-dsw--0-ia5     19-Oct-2019 17:33                1843
ber01-VHDL13_DWLH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1815
ber01-VHDL13_DWLH_191933-1910191933-dsw--0-ia5     19-Oct-2019 19:33                1843
ber01-VHDL13_DWLH_192033-1910192033-dsw--0-ia5     19-Oct-2019 20:33                1843
ber01-VHDL13_DWLH_200033-1910200033-dsw--0-ia5     20-Oct-2019 00:33                2012
ber01-VHDL13_DWLH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2075
ber01-VHDL13_DWLH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2035
ber01-VHDL13_DWLH_200533-1910200533-dsw--0-ia5     20-Oct-2019 05:33                2063
ber01-VHDL13_DWLH_200633-1910200633-dsw--0-ia5     20-Oct-2019 06:33                2063
ber01-VHDL13_DWLH_200733-1910200733-dsw--0-ia5     20-Oct-2019 07:33                2063
ber01-VHDL13_DWLH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2034
ber01-VHDL13_DWLH_200933-1910200933-dsw--0-ia5     20-Oct-2019 09:33                1998
ber01-VHDL13_DWLH_201033-1910201033-dsw--0-ia5     20-Oct-2019 10:33                1998
ber01-VHDL13_DWLH_201133-1910201133-dsw--0-ia5     20-Oct-2019 11:33                1998
ber01-VHDL13_DWLH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2003
ber01-VHDL13_DWLH_201333-1910201333-dsw--0-ia5     20-Oct-2019 13:33                2031
ber01-VHDL13_DWLH_201433-1910201433-dsw--0-ia5     20-Oct-2019 14:33                2025
ber01-VHDL13_DWLH_201533-1910201533-dsw--0-ia5     20-Oct-2019 15:33                2025
ber01-VHDL13_DWLH_201633-1910201633-dsw--0-ia5     20-Oct-2019 16:33                1955
ber01-VHDL13_DWLH_201733-1910201733-dsw--0-ia5     20-Oct-2019 17:33                1670
ber01-VHDL13_DWLH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1642
ber01-VHDL13_DWLH_201933-1910201933-dsw--0-ia5     20-Oct-2019 19:33                1670
ber01-VHDL13_DWLH_202033-1910202033-dsw--0-ia5     20-Oct-2019 20:33                1670
ber01-VHDL13_DWLH_210033-1910210033-dsw--0-ia5     21-Oct-2019 00:33                1885
ber01-VHDL13_DWLH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                1851
ber01-VHDL13_DWLH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                1917
ber01-VHDL13_DWLH_210533-1910210533-dsw--0-ia5     21-Oct-2019 05:33                1949
ber01-VHDL13_DWLH_210633-1910210633-dsw--0-ia5     21-Oct-2019 06:33                2334
ber01-VHDL13_DWLH_210733-1910210733-dsw--0-ia5     21-Oct-2019 07:33                2331
ber01-VHDL13_DWLH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2303
ber01-VHDL13_DWLH_210933-1910210933-dsw--0-ia5     21-Oct-2019 09:33                2331
ber01-VHDL13_DWLH_211033-1910211033-dsw--0-ia5     21-Oct-2019 10:33                2331
ber01-VHDL13_DWLH_211133-1910211133-dsw--0-ia5     21-Oct-2019 11:33                2329
ber01-VHDL13_DWLH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2293
ber01-VHDL13_DWLH_211333-1910211333-dsw--0-ia5     21-Oct-2019 13:33                2252
ber01-VHDL13_DWLH_211433-1910211433-dsw--0-ia5     21-Oct-2019 14:33                2252
ber01-VHDL13_DWLH_211533-1910211533-dsw--0-ia5     21-Oct-2019 15:33                2252
ber01-VHDL13_DWLH_211633-1910211633-dsw--0-ia5     21-Oct-2019 16:33                2252
ber01-VHDL13_DWLI_191733-1910191733-dsw--0-ia5     19-Oct-2019 17:33                1831
ber01-VHDL13_DWLI_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1803
ber01-VHDL13_DWLI_191933-1910191933-dsw--0-ia5     19-Oct-2019 19:33                1831
ber01-VHDL13_DWLI_192033-1910192033-dsw--0-ia5     19-Oct-2019 20:33                1831
ber01-VHDL13_DWLI_200033-1910200033-dsw--0-ia5     20-Oct-2019 00:33                2027
ber01-VHDL13_DWLI_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2086
ber01-VHDL13_DWLI_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2046
ber01-VHDL13_DWLI_200533-1910200533-dsw--0-ia5     20-Oct-2019 05:33                2074
ber01-VHDL13_DWLI_200633-1910200633-dsw--0-ia5     20-Oct-2019 06:33                2074
ber01-VHDL13_DWLI_200733-1910200733-dsw--0-ia5     20-Oct-2019 07:33                2074
ber01-VHDL13_DWLI_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2045
ber01-VHDL13_DWLI_200933-1910200933-dsw--0-ia5     20-Oct-2019 09:33                2011
ber01-VHDL13_DWLI_201033-1910201033-dsw--0-ia5     20-Oct-2019 10:33                2011
ber01-VHDL13_DWLI_201133-1910201133-dsw--0-ia5     20-Oct-2019 11:33                2011
ber01-VHDL13_DWLI_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2004
ber01-VHDL13_DWLI_201333-1910201333-dsw--0-ia5     20-Oct-2019 13:33                2032
ber01-VHDL13_DWLI_201433-1910201433-dsw--0-ia5     20-Oct-2019 14:33                2019
ber01-VHDL13_DWLI_201533-1910201533-dsw--0-ia5     20-Oct-2019 15:33                2019
ber01-VHDL13_DWLI_201633-1910201633-dsw--0-ia5     20-Oct-2019 16:33                1963
ber01-VHDL13_DWLI_201733-1910201733-dsw--0-ia5     20-Oct-2019 17:33                1669
ber01-VHDL13_DWLI_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1641
ber01-VHDL13_DWLI_201933-1910201933-dsw--0-ia5     20-Oct-2019 19:33                1669
ber01-VHDL13_DWLI_202033-1910202033-dsw--0-ia5     20-Oct-2019 20:33                1669
ber01-VHDL13_DWLI_210033-1910210033-dsw--0-ia5     21-Oct-2019 00:33                1895
ber01-VHDL13_DWLI_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                1857
ber01-VHDL13_DWLI_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                1901
ber01-VHDL13_DWLI_210533-1910210533-dsw--0-ia5     21-Oct-2019 05:33                1933
ber01-VHDL13_DWLI_210633-1910210633-dsw--0-ia5     21-Oct-2019 06:33                2028
ber01-VHDL13_DWLI_210733-1910210733-dsw--0-ia5     21-Oct-2019 07:33                2026
ber01-VHDL13_DWLI_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1998
ber01-VHDL13_DWLI_210933-1910210933-dsw--0-ia5     21-Oct-2019 09:33                2026
ber01-VHDL13_DWLI_211033-1910211033-dsw--0-ia5     21-Oct-2019 10:33                2026
ber01-VHDL13_DWLI_211133-1910211133-dsw--0-ia5     21-Oct-2019 11:33                2059
ber01-VHDL13_DWLI_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2023
ber01-VHDL13_DWLI_211333-1910211333-dsw--0-ia5     21-Oct-2019 13:33                1945
ber01-VHDL13_DWLI_211433-1910211433-dsw--0-ia5     21-Oct-2019 14:33                1945
ber01-VHDL13_DWLI_211533-1910211533-dsw--0-ia5     21-Oct-2019 15:33                1945
ber01-VHDL13_DWLI_211633-1910211633-dsw--0-ia5     21-Oct-2019 16:33                1945
ber01-VHDL13_DWMG_191700-1910191700-dsw--0-ia5     19-Oct-2019 17:30                2630
ber01-VHDL13_DWMG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2653
ber01-VHDL13_DWMG_191900-1910191900-dsw--0-ia5     19-Oct-2019 19:30                2820
ber01-VHDL13_DWMG_192000-1910192000-dsw--0-ia5     19-Oct-2019 20:30                2820
ber01-VHDL13_DWMG_192100-1910192100-dsw--0-ia5     19-Oct-2019 21:30                2756
ber01-VHDL13_DWMG_192200-1910192200-dsw--0-ia5     19-Oct-2019 22:30                2894
ber01-VHDL13_DWMG_192300-1910192300-dsw--0-ia5     19-Oct-2019 23:30                2894
ber01-VHDL13_DWMG_200000-1910200000-dsw--0-ia5     20-Oct-2019 00:30                2894
ber01-VHDL13_DWMG_200100-1910200100-dsw--0-ia5     20-Oct-2019 01:30                2894
ber01-VHDL13_DWMG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2660
ber01-VHDL13_DWMG_200300-1910200300-dsw--0-ia5     20-Oct-2019 03:30                2660
ber01-VHDL13_DWMG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2560
ber01-VHDL13_DWMG_200500-1910200500-dsw--0-ia5     20-Oct-2019 05:30                2560
ber01-VHDL13_DWMG_200600-1910200600-dsw--0-ia5     20-Oct-2019 06:30                2560
ber01-VHDL13_DWMG_200700-1910200700-dsw--0-ia5     20-Oct-2019 07:30                2560
ber01-VHDL13_DWMG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2459
ber01-VHDL13_DWMG_200900-1910200900-dsw--0-ia5     20-Oct-2019 09:30                2459
ber01-VHDL13_DWMG_201000-1910201000-dsw--0-ia5     20-Oct-2019 10:30                2459
ber01-VHDL13_DWMG_201100-1910201100-dsw--0-ia5     20-Oct-2019 11:30                2459
ber01-VHDL13_DWMG_201200-1910201200-dsw--0-ia5     20-Oct-2019 12:30                2377
ber01-VHDL13_DWMG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2377
ber01-VHDL13_DWMG_201400-1910201400-dsw--0-ia5     20-Oct-2019 14:30                2248
ber01-VHDL13_DWMG_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                2248
ber01-VHDL13_DWMG_201600-1910201600-dsw--0-ia5     20-Oct-2019 16:30                2248
ber01-VHDL13_DWMG_201700-1910201700-dsw--0-ia5     20-Oct-2019 17:30                2088
ber01-VHDL13_DWMG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                2327
ber01-VHDL13_DWMG_201900-1910201900-dsw--0-ia5     20-Oct-2019 19:30                2361
ber01-VHDL13_DWMG_202000-1910202000-dsw--0-ia5     20-Oct-2019 20:30                2369
ber01-VHDL13_DWMG_202100-1910202100-dsw--0-ia5     20-Oct-2019 21:30                2418
ber01-VHDL13_DWMG_202200-1910202200-dsw--0-ia5     20-Oct-2019 22:30                2484
ber01-VHDL13_DWMG_202300-1910202300-dsw--0-ia5     20-Oct-2019 23:30                2484
ber01-VHDL13_DWMG_210000-1910210000-dsw--0-ia5     21-Oct-2019 00:30                2484
ber01-VHDL13_DWMG_210100-1910210100-dsw--0-ia5     21-Oct-2019 01:30                2484
ber01-VHDL13_DWMG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2386
ber01-VHDL13_DWMG_210300-1910210300-dsw--0-ia5     21-Oct-2019 03:30                2386
ber01-VHDL13_DWMG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2176
ber01-VHDL13_DWMG_210500-1910210500-dsw--0-ia5     21-Oct-2019 05:30                2263
ber01-VHDL13_DWMG_210600-1910210600-dsw--0-ia5     21-Oct-2019 06:30                2263
ber01-VHDL13_DWMG_210700-1910210700-dsw--0-ia5     21-Oct-2019 07:30                2210
ber01-VHDL13_DWMG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2169
ber01-VHDL13_DWMG_210900-1910210900-dsw--0-ia5     21-Oct-2019 09:30                2161
ber01-VHDL13_DWMG_211000-1910211000-dsw--0-ia5     21-Oct-2019 10:30                2191
ber01-VHDL13_DWMG_211100-1910211100-dsw--0-ia5     21-Oct-2019 11:30                2191
ber01-VHDL13_DWMG_211200-1910211200-dsw--0-ia5     21-Oct-2019 12:30                2368
ber01-VHDL13_DWMG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2368
ber01-VHDL13_DWMG_211400-1910211400-dsw--0-ia5     21-Oct-2019 14:30                2368
ber01-VHDL13_DWMG_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                2364
ber01-VHDL13_DWMG_211600-1910211600-dsw--0-ia5     21-Oct-2019 16:30                2364
ber01-VHDL13_DWMO_191700-1910191700-dsw--0-ia5     19-Oct-2019 17:30                2088
ber01-VHDL13_DWMO_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2090
ber01-VHDL13_DWMO_191900-1910191900-dsw--0-ia5     19-Oct-2019 19:30                2259
ber01-VHDL13_DWMO_192000-1910192000-dsw--0-ia5     19-Oct-2019 20:30                2259
ber01-VHDL13_DWMO_192100-1910192100-dsw--0-ia5     19-Oct-2019 21:30                2203
ber01-VHDL13_DWMO_192200-1910192200-dsw--0-ia5     19-Oct-2019 22:30                2387
ber01-VHDL13_DWMO_192300-1910192300-dsw--0-ia5     19-Oct-2019 23:30                2387
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ber01-VHDL13_DWMO_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2157
ber01-VHDL13_DWMO_200900-1910200900-dsw--0-ia5     20-Oct-2019 09:30                2129
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ber01-VHDL13_DWMO_201200-1910201200-dsw--0-ia5     20-Oct-2019 12:30                1998
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ber01-VHDL13_DWMO_201600-1910201600-dsw--0-ia5     20-Oct-2019 16:30                1862
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ber01-VHDL13_DWMO_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1759
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ber01-VHDL13_DWMO_211200-1910211200-dsw--0-ia5     21-Oct-2019 12:30                2199
ber01-VHDL13_DWMO_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2199
ber01-VHDL13_DWMO_211400-1910211400-dsw--0-ia5     21-Oct-2019 14:30                2199
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ber01-VHDL13_DWMP_191700-1910191700-dsw--0-ia5     19-Oct-2019 17:30                2543
ber01-VHDL13_DWMP_191900-1910191900-dsw--0-ia5     19-Oct-2019 19:30                2545
ber01-VHDL13_DWMP_192000-1910192000-dsw--0-ia5     19-Oct-2019 20:30                2545
ber01-VHDL13_DWMP_192100-1910192100-dsw--0-ia5     19-Oct-2019 21:30                2820
ber01-VHDL13_DWMP_192200-1910192200-dsw--0-ia5     19-Oct-2019 22:30                3180
ber01-VHDL13_DWMP_192300-1910192300-dsw--0-ia5     19-Oct-2019 23:30                3180
ber01-VHDL13_DWMP_200000-1910200000-dsw--0-ia5     20-Oct-2019 00:30                3180
ber01-VHDL13_DWMP_200100-1910200100-dsw--0-ia5     20-Oct-2019 01:30                3180
ber01-VHDL13_DWMP_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2888
ber01-VHDL13_DWMP_200300-1910200300-dsw--0-ia5     20-Oct-2019 03:30                2888
ber01-VHDL13_DWMP_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2875
ber01-VHDL13_DWMP_200500-1910200500-dsw--0-ia5     20-Oct-2019 05:30                2875
ber01-VHDL13_DWMP_200600-1910200600-dsw--0-ia5     20-Oct-2019 06:30                2875
ber01-VHDL13_DWMP_200700-1910200700-dsw--0-ia5     20-Oct-2019 07:30                2875
ber01-VHDL13_DWMP_200800-1910200800-dsw--0-ia5     20-Oct-2019 12:30                2666
ber01-VHDL13_DWMP_200900-1910200900-dsw--0-ia5     20-Oct-2019 09:30                2722
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ber01-VHDL13_DWMP_201100-1910201100-dsw--0-ia5     20-Oct-2019 11:30                2722
ber01-VHDL13_DWMP_201200-1910201200-dsw--0-ia5     20-Oct-2019 12:30                2666
ber01-VHDL13_DWMP_201400-1910201400-dsw--0-ia5     20-Oct-2019 14:30                2666
ber01-VHDL13_DWMP_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                2495
ber01-VHDL13_DWMP_201600-1910201600-dsw--0-ia5     20-Oct-2019 16:30                2495
ber01-VHDL13_DWMP_201700-1910201700-dsw--0-ia5     20-Oct-2019 17:30                2336
ber01-VHDL13_DWMP_201900-1910201900-dsw--0-ia5     20-Oct-2019 19:30                2432
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ber01-VHDL13_DWMP_202100-1910202100-dsw--0-ia5     20-Oct-2019 21:30                2374
ber01-VHDL13_DWMP_202200-1910202200-dsw--0-ia5     20-Oct-2019 22:30                2561
ber01-VHDL13_DWMP_202300-1910202300-dsw--0-ia5     20-Oct-2019 23:30                2561
ber01-VHDL13_DWMP_210000-1910210000-dsw--0-ia5     21-Oct-2019 00:30                2561
ber01-VHDL13_DWMP_210100-1910210100-dsw--0-ia5     21-Oct-2019 01:30                2561
ber01-VHDL13_DWMP_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2461
ber01-VHDL13_DWMP_210300-1910210300-dsw--0-ia5     21-Oct-2019 03:30                2461
ber01-VHDL13_DWMP_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2304
ber01-VHDL13_DWMP_210500-1910210500-dsw--0-ia5     21-Oct-2019 05:30                2314
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ber01-VHDL13_DWMP_210700-1910210700-dsw--0-ia5     21-Oct-2019 07:30                2314
ber01-VHDL13_DWMP_210800-1910210800-dsw--0-ia5     21-Oct-2019 12:30                2477
ber01-VHDL13_DWMP_210900-1910210900-dsw--0-ia5     21-Oct-2019 09:30                2296
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ber01-VHDL13_DWMP_211200-1910211200-dsw--0-ia5     21-Oct-2019 12:30                2477
ber01-VHDL13_DWMP_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:35                2477
ber01-VHDL13_DWMP_211400-1910211400-dsw--0-ia5     21-Oct-2019 14:30                2477
ber01-VHDL13_DWMP_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                2406
ber01-VHDL13_DWMP_211600-1910211600-dsw--0-ia5     21-Oct-2019 16:30                2406
ber01-VHDL13_DWOG_191700-1910191700-dsw--0-ia5     19-Oct-2019 17:30                4949
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ber01-VHDL13_DWOG_200300-1910200300-dsw--0-ia5     20-Oct-2019 03:00                4813
ber01-VHDL13_DWOG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:15                4805
ber01-VHDL13_DWOG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:00                4658
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ber01-VHDL13_DWOG_210100-1910210100-dsw--0-ia5     21-Oct-2019 01:45                4272
ber01-VHDL13_DWOG_210300-1910210300-dsw--0-ia5     21-Oct-2019 03:00                4343
ber01-VHDL13_DWOG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:15                4259
ber01-VHDL13_DWOG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:00                4118
ber01-VHDL13_DWOH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:28                1892
ber01-VHDL13_DWOH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:28                2165
ber01-VHDL13_DWOH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:58                2043
ber01-VHDL13_DWOH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:28                2043
ber01-VHDL13_DWOH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:28                2076
ber01-VHDL13_DWOH_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:28                2061
ber01-VHDL13_DWOH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:28                1902
ber01-VHDL13_DWOH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:28                2123
ber01-VHDL13_DWOH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:58                2094
ber01-VHDL13_DWOH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:28                2062
ber01-VHDL13_DWOH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:28                1989
ber01-VHDL13_DWOH_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:28                1943
ber01-VHDL13_DWOI_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:28                2367
ber01-VHDL13_DWOI_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:28                2462
ber01-VHDL13_DWOI_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:58                2503
ber01-VHDL13_DWOI_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:28                2509
ber01-VHDL13_DWOI_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:28                2539
ber01-VHDL13_DWOI_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:28                2588
ber01-VHDL13_DWOI_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:28                2287
ber01-VHDL13_DWOI_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:28                2218
ber01-VHDL13_DWOI_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:58                2179
ber01-VHDL13_DWOI_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:28                2155
ber01-VHDL13_DWOI_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:28                2048
ber01-VHDL13_DWOI_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:28                2092
ber01-VHDL13_DWON_191705-1910191705-dsw--0-ia5     19-Oct-2019 17:05                4326
ber01-VHDL13_DWON_192002-1910192002-dsw--0-ia5     19-Oct-2019 20:02                4218
ber01-VHDL13_DWON_200041-1910200041-dsw--0-ia5     20-Oct-2019 00:41                4404
ber01-VHDL13_DWON_200042-1910200042-dsw--0-ia5     20-Oct-2019 00:42                4404
ber01-VHDL13_DWON_200046-1910200046-dsw--0-ia5     20-Oct-2019 00:46                4404
ber01-VHDL13_DWON_200255-1910200255-dsw--0-ia5     20-Oct-2019 02:55                4412
ber01-VHDL13_DWON_200256-1910200256-dsw--0-ia5     20-Oct-2019 02:56                4412
ber01-VHDL13_DWON_200519-1910200519-dsw--0-ia5     20-Oct-2019 05:19                4660
ber01-VHDL13_DWON_200820-1910200820-dsw--0-ia5     20-Oct-2019 08:20                4899
ber01-VHDL13_DWON_201122-1910201122-dsw--0-ia5     20-Oct-2019 11:22                4847
ber01-VHDL13_DWON_201336-1910201336-dsw--0-ia5     20-Oct-2019 13:36                4789
ber01-VHDL13_DWON_201415-1910201415-dsw--0-ia5     20-Oct-2019 14:16                4417
ber01-VHDL13_DWON_201416-1910201416-dsw--0-ia5     20-Oct-2019 14:16                4417
ber01-VHDL13_DWON_201440-1910201440-dsw--0-ia5     20-Oct-2019 14:40                3893
ber01-VHDL13_DWON_201708-1910201708-dsw--0-ia5     20-Oct-2019 17:08                3885
ber01-VHDL13_DWON_201715-1910201715-dsw--0-ia5     20-Oct-2019 17:15                3969
ber01-VHDL13_DWON_201912-1910201912-dsw--0-ia5     20-Oct-2019 19:12                4017
ber01-VHDL13_DWON_210032-1910210032-dsw--0-ia5     21-Oct-2019 00:32                4676
ber01-VHDL13_DWON_210220-1910210220-dsw--0-ia5     21-Oct-2019 02:20                4676
ber01-VHDL13_DWON_210253-1910210253-dsw--0-ia5     21-Oct-2019 02:53                4716
ber01-VHDL13_DWON_210530-1910210530-dsw--0-ia5     21-Oct-2019 05:30                4266
ber01-VHDL13_DWON_210536-1910210536-dsw--0-ia5     21-Oct-2019 05:36                4266
ber01-VHDL13_DWON_210659-1910210659-dsw--0-ia5     21-Oct-2019 06:59                3989
ber01-VHDL13_DWON_211150-1910211150-dsw--0-ia5     21-Oct-2019 11:50                4326
ber01-VHDL13_DWON_211448-1910211448-dsw--0-ia5     21-Oct-2019 14:48                3793
ber01-VHDL13_DWPG_191730-1910191730-dsw--0-ia5     19-Oct-2019 17:30                2208
ber01-VHDL13_DWPG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2118
ber01-VHDL13_DWPG_191930-1910191930-dsw--0-ia5     19-Oct-2019 19:30                2117
ber01-VHDL13_DWPG_192030-1910192030-dsw--0-ia5     19-Oct-2019 20:30                2117
ber01-VHDL13_DWPG_200030-1910200030-dsw--0-ia5     20-Oct-2019 00:30                2259
ber01-VHDL13_DWPG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2290
ber01-VHDL13_DWPG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2224
ber01-VHDL13_DWPG_200530-1910200530-dsw--0-ia5     20-Oct-2019 05:30                2222
ber01-VHDL13_DWPG_200630-1910200630-dsw--0-ia5     20-Oct-2019 06:30                2222
ber01-VHDL13_DWPG_200730-1910200730-dsw--0-ia5     20-Oct-2019 07:30                2222
ber01-VHDL13_DWPG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                1940
ber01-VHDL13_DWPG_200930-1910200930-dsw--0-ia5     20-Oct-2019 09:30                1939
ber01-VHDL13_DWPG_201030-1910201030-dsw--0-ia5     20-Oct-2019 10:30                1939
ber01-VHDL13_DWPG_201130-1910201130-dsw--0-ia5     20-Oct-2019 11:30                1903
ber01-VHDL13_DWPG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                1900
ber01-VHDL13_DWPG_201330-1910201330-dsw--0-ia5     20-Oct-2019 13:30                1907
ber01-VHDL13_DWPG_201430-1910201430-dsw--0-ia5     20-Oct-2019 14:30                1907
ber01-VHDL13_DWPG_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                1928
ber01-VHDL13_DWPG_201630-1910201630-dsw--0-ia5     20-Oct-2019 16:30                1934
ber01-VHDL13_DWPG_201730-1910201730-dsw--0-ia5     20-Oct-2019 17:30                1934
ber01-VHDL13_DWPG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1919
ber01-VHDL13_DWPG_201930-1910201930-dsw--0-ia5     20-Oct-2019 19:30                1918
ber01-VHDL13_DWPG_202030-1910202030-dsw--0-ia5     20-Oct-2019 20:30                1918
ber01-VHDL13_DWPG_210030-1910210030-dsw--0-ia5     21-Oct-2019 00:30                1927
ber01-VHDL13_DWPG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                1931
ber01-VHDL13_DWPG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                1929
ber01-VHDL13_DWPG_210530-1910210530-dsw--0-ia5     21-Oct-2019 05:30                1999
ber01-VHDL13_DWPG_210630-1910210630-dsw--0-ia5     21-Oct-2019 06:30                1999
ber01-VHDL13_DWPG_210730-1910210730-dsw--0-ia5     21-Oct-2019 07:30                1999
ber01-VHDL13_DWPG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1960
ber01-VHDL13_DWPG_210930-1910210930-dsw--0-ia5     21-Oct-2019 09:30                1959
ber01-VHDL13_DWPG_211030-1910211030-dsw--0-ia5     21-Oct-2019 10:30                1959
ber01-VHDL13_DWPG_211130-1910211130-dsw--0-ia5     21-Oct-2019 11:30                1904
ber01-VHDL13_DWPG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                1889
ber01-VHDL13_DWPG_211330-1910211330-dsw--0-ia5     21-Oct-2019 13:30                1888
ber01-VHDL13_DWPG_211430-1910211430-dsw--0-ia5     21-Oct-2019 14:30                1888
ber01-VHDL13_DWPG_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                1955
ber01-VHDL13_DWPG_211630-1910211630-dsw--0-ia5     21-Oct-2019 16:30                1954
ber01-VHDL13_DWPH_191730-1910191730-dsw--0-ia5     19-Oct-2019 17:30                2202
ber01-VHDL13_DWPH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1970
ber01-VHDL13_DWPH_191930-1910191930-dsw--0-ia5     19-Oct-2019 19:30                1970
ber01-VHDL13_DWPH_192030-1910192030-dsw--0-ia5     19-Oct-2019 20:30                1970
ber01-VHDL13_DWPH_200030-1910200030-dsw--0-ia5     20-Oct-2019 00:30                2096
ber01-VHDL13_DWPH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2170
ber01-VHDL13_DWPH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1968
ber01-VHDL13_DWPH_200530-1910200530-dsw--0-ia5     20-Oct-2019 05:30                1968
ber01-VHDL13_DWPH_200630-1910200630-dsw--0-ia5     20-Oct-2019 06:30                1968
ber01-VHDL13_DWPH_200730-1910200730-dsw--0-ia5     20-Oct-2019 07:30                1968
ber01-VHDL13_DWPH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2015
ber01-VHDL13_DWPH_200930-1910200930-dsw--0-ia5     20-Oct-2019 09:30                2015
ber01-VHDL13_DWPH_201030-1910201030-dsw--0-ia5     20-Oct-2019 10:30                2015
ber01-VHDL13_DWPH_201130-1910201130-dsw--0-ia5     20-Oct-2019 11:30                1997
ber01-VHDL13_DWPH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2033
ber01-VHDL13_DWPH_201330-1910201330-dsw--0-ia5     20-Oct-2019 13:30                2048
ber01-VHDL13_DWPH_201430-1910201430-dsw--0-ia5     20-Oct-2019 14:30                2048
ber01-VHDL13_DWPH_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                1952
ber01-VHDL13_DWPH_201630-1910201630-dsw--0-ia5     20-Oct-2019 16:30                1952
ber01-VHDL13_DWPH_201730-1910201730-dsw--0-ia5     20-Oct-2019 17:30                1952
ber01-VHDL13_DWPH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1769
ber01-VHDL13_DWPH_201930-1910201930-dsw--0-ia5     20-Oct-2019 19:30                1769
ber01-VHDL13_DWPH_202030-1910202030-dsw--0-ia5     20-Oct-2019 20:30                1769
ber01-VHDL13_DWPH_210030-1910210030-dsw--0-ia5     21-Oct-2019 00:30                2093
ber01-VHDL13_DWPH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2087
ber01-VHDL13_DWPH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2099
ber01-VHDL13_DWPH_210530-1910210530-dsw--0-ia5     21-Oct-2019 05:30                2099
ber01-VHDL13_DWPH_210630-1910210630-dsw--0-ia5     21-Oct-2019 06:30                2099
ber01-VHDL13_DWPH_210730-1910210730-dsw--0-ia5     21-Oct-2019 07:30                2099
ber01-VHDL13_DWPH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1956
ber01-VHDL13_DWPH_210930-1910210930-dsw--0-ia5     21-Oct-2019 09:30                1956
ber01-VHDL13_DWPH_211030-1910211030-dsw--0-ia5     21-Oct-2019 10:30                2019
ber01-VHDL13_DWPH_211130-1910211130-dsw--0-ia5     21-Oct-2019 11:30                2033
ber01-VHDL13_DWPH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                1978
ber01-VHDL13_DWPH_211330-1910211330-dsw--0-ia5     21-Oct-2019 13:30                1978
ber01-VHDL13_DWPH_211430-1910211430-dsw--0-ia5     21-Oct-2019 14:30                1978
ber01-VHDL13_DWPH_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                1878
ber01-VHDL13_DWPH_211630-1910211630-dsw--0-ia5     21-Oct-2019 16:30                1878
ber01-VHDL13_DWSG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2381
ber01-VHDL13_DWSG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2442
ber01-VHDL13_DWSG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2373
ber01-VHDL13_DWSG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2317
ber01-VHDL13_DWSG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2417
ber01-VHDL13_DWSG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                2070
ber01-VHDL13_DWSG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2019
ber01-VHDL13_DWSG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2114
ber01-VHDL13_DWSG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2019
ber01-VHDL13_DWSG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2079
ber01-VHDL13_DWSN_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1811
ber01-VHDL13_DWSN_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                1886
ber01-VHDL13_DWSN_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1913
ber01-VHDL13_DWSN_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                1898
ber01-VHDL13_DWSN_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:30                1987
ber01-VHDL13_DWSN_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1791
ber01-VHDL13_DWSN_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2028
ber01-VHDL13_DWSN_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2122
ber01-VHDL13_DWSN_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1997
ber01-VHDL13_DWSN_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:30                2002
ber01-VHDL13_DWSO_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                1912
ber01-VHDL13_DWSO_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2015
ber01-VHDL13_DWSO_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                1862
ber01-VHDL13_DWSO_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                1832
ber01-VHDL13_DWSO_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:30                1865
ber01-VHDL13_DWSO_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1512
ber01-VHDL13_DWSO_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                1801
ber01-VHDL13_DWSO_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                1948
ber01-VHDL13_DWSO_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                1980
ber01-VHDL13_DWSO_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:30                1971
ber01-VHDL13_DWSP_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2084
ber01-VHDL13_DWSP_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                2157
ber01-VHDL13_DWSP_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2199
ber01-VHDL13_DWSP_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2118
ber01-VHDL13_DWSP_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:30                2090
ber01-VHDL13_DWSP_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                1948
ber01-VHDL13_DWSP_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2154
ber01-VHDL13_DWSP_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                2163
ber01-VHDL13_DWSP_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2025
ber01-VHDL13_DWSP_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:30                1966
ber01-VHDL17_DWOG_201200-1910201200-dsw--0-ia5     20-Oct-2019 10:01                3383
ber01-VHDL17_DWOG_211200-1910211200-dsw--0-ia5     21-Oct-2019 10:52                2342
ber01-VHDL20_DWHG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3416
ber01-VHDL20_DWHG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3636
ber01-VHDL20_DWHG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                3635
ber01-VHDL20_DWHG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4293
ber01-VHDL20_DWHG_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:45                4290
ber01-VHDL20_DWHG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                4163
ber01-VHDL20_DWHG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                4137
ber01-VHDL20_DWHG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3962
ber01-VHDL20_DWHG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                4008
ber01-VHDL20_DWHG_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:45                3964
ber01-VHDL20_DWHH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                2860
ber01-VHDL20_DWHH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                2736
ber01-VHDL20_DWHH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                2730
ber01-VHDL20_DWHH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3347
ber01-VHDL20_DWHH_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:45                3326
ber01-VHDL20_DWHH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3188
ber01-VHDL20_DWHH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3156
ber01-VHDL20_DWHH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3147
ber01-VHDL20_DWHH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3143
ber01-VHDL20_DWHH_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:45                3353
gts01-VHDL12_DWON_191815-1910191745-afsv--22-ia5   19-Oct-2019 17:45                3858
gts01-VHDL12_DWON_200115-1910200145-afsv--60-ia5   20-Oct-2019 01:45                3795
gts01-VHDL12_DWON_200530-1910200530-afsv--90-ia5   20-Oct-2019 05:30                4058
gts01-VHDL12_DWON_200815-1910200815-afsv--67-ia5   20-Oct-2019 08:15                4058
gts01-VHDL12_DWON_201330-1910201230-afsv--15-ia5   20-Oct-2019 12:30                4247
gts01-VHDL12_DWON_201815-1910201745-afsv--69-ia5   20-Oct-2019 17:45                3342
gts01-VHDL12_DWON_210115-1910210145-afsv--96-ia5   21-Oct-2019 01:45                4178
gts01-VHDL12_DWON_210530-1910210530-afsv--29-ia5   21-Oct-2019 05:30                4223
gts01-VHDL12_DWON_210815-1910210815-afsv--13-ia5   21-Oct-2019 08:15                3380
gts01-VHDL12_DWON_211330-1910211230-afsv--79-ia5   21-Oct-2019 12:30                3725
pid-VHDL12_DWEH_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:28                1629
pid-VHDL12_DWEH_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:28                1818
pid-VHDL12_DWHG_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                1591
pid-VHDL12_DWHG_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                1598
pid-VHDL12_DWHG_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                2010
pid-VHDL12_DWHG_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1841
pid-VHDL12_DWHH_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                1414
pid-VHDL12_DWHH_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                1416
pid-VHDL12_DWHH_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                1811
pid-VHDL12_DWHH_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1810
pid-VHDL12_DWLG_191800-1910191800-dsw--0-ia5       19-Oct-2019 18:30                1309
pid-VHDL12_DWLG_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                1491
pid-VHDL12_DWLG_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                1504
pid-VHDL12_DWLG_200800-1910200800-dsw--0-ia5       20-Oct-2019 08:30                1501
pid-VHDL12_DWLG_201300-1910201300-dsw--0-ia5       20-Oct-2019 12:30                1445
pid-VHDL12_DWLG_201800-1910201800-dsw--0-ia5       20-Oct-2019 18:30                1200
pid-VHDL12_DWLG_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                1617
pid-VHDL12_DWLG_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1658
pid-VHDL12_DWLG_210800-1910210800-dsw--0-ia5       21-Oct-2019 08:30                1749
pid-VHDL12_DWLG_211300-1910211300-dsw--0-ia5       21-Oct-2019 12:30                1736
pid-VHDL12_DWLH_191800-1910191800-dsw--0-ia5       19-Oct-2019 18:30                1503
pid-VHDL12_DWLH_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                1710
pid-VHDL12_DWLH_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                1670
pid-VHDL12_DWLH_200800-1910200800-dsw--0-ia5       20-Oct-2019 08:30                1669
pid-VHDL12_DWLH_201300-1910201300-dsw--0-ia5       20-Oct-2019 12:30                1638
pid-VHDL12_DWLH_201800-1910201800-dsw--0-ia5       20-Oct-2019 18:30                1277
pid-VHDL12_DWLH_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                1601
pid-VHDL12_DWLH_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1666
pid-VHDL12_DWLH_210800-1910210800-dsw--0-ia5       21-Oct-2019 08:30                2001
pid-VHDL12_DWLH_211300-1910211300-dsw--0-ia5       21-Oct-2019 12:30                1991
pid-VHDL12_DWLI_191800-1910191800-dsw--0-ia5       19-Oct-2019 18:30                1482
pid-VHDL12_DWLI_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                1722
pid-VHDL12_DWLI_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                1682
pid-VHDL12_DWLI_200800-1910200800-dsw--0-ia5       20-Oct-2019 08:30                1681
pid-VHDL12_DWLI_201300-1910201300-dsw--0-ia5       20-Oct-2019 12:30                1640
pid-VHDL12_DWLI_201800-1910201800-dsw--0-ia5       20-Oct-2019 18:30                1277
pid-VHDL12_DWLI_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                1601
pid-VHDL12_DWLI_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1651
pid-VHDL12_DWLI_210800-1910210800-dsw--0-ia5       21-Oct-2019 08:30                1747
pid-VHDL12_DWLI_211300-1910211300-dsw--0-ia5       21-Oct-2019 12:30                1772
pid-VHDL12_DWMG_191800-1910191800-dsw--0-ia5       19-Oct-2019 18:30                2377
pid-VHDL12_DWMG_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                2273
pid-VHDL12_DWMG_200400-1910200400-dsw--0-ia5       20-Oct-2019 04:30                2173
pid-VHDL12_DWMG_200800-1910200800-dsw--0-ia5       20-Oct-2019 08:30                2072
pid-VHDL12_DWMG_201300-1910201300-dsw--0-ia5       20-Oct-2019 12:30                1990
pid-VHDL12_DWMG_201800-1910201800-dsw--0-ia5       20-Oct-2019 18:30                1940
pid-VHDL12_DWMG_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                2113
pid-VHDL12_DWMG_210400-1910210400-dsw--0-ia5       21-Oct-2019 04:30                1903
pid-VHDL12_DWMG_210800-1910210800-dsw--0-ia5       21-Oct-2019 08:30                1896
pid-VHDL12_DWMG_211300-1910211300-dsw--0-ia5       21-Oct-2019 12:30                2095
pid-VHDL12_DWOG_200100-1910200100-dsw--0-ia5       20-Oct-2019 01:45                4118
pid-VHDL12_DWOG_200300-1910200300-dsw--0-ia5       20-Oct-2019 03:00                4081
pid-VHDL12_DWOG_210100-1910210100-dsw--0-ia5       21-Oct-2019 01:45                3653
pid-VHDL12_DWOG_210300-1910210300-dsw--0-ia5       21-Oct-2019 03:00                3724
pid-VHDL12_DWOH_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:28                1787
pid-VHDL12_DWOH_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:28                1832
pid-VHDL12_DWOI_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:28                2085
pid-VHDL12_DWOI_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:28                1928
pid-VHDL12_DWSG_200200-1910200200-dsw--0-ia5       20-Oct-2019 02:30                2184
pid-VHDL12_DWSG_210200-1910210200-dsw--0-ia5       21-Oct-2019 02:30                1647
swis2-VHDL20_DWEG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3702
swis2-VHDL20_DWEG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3923
swis2-VHDL20_DWEG_200400-1910200400-dsw--0-ia5     20-Oct-2019 05:15                3858
swis2-VHDL20_DWEG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3861
swis2-VHDL20_DWEG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                3894
swis2-VHDL20_DWEG_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:45                3879
swis2-VHDL20_DWEG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3727
swis2-VHDL20_DWEG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3896
swis2-VHDL20_DWEG_210400-1910210400-dsw--0-ia5     21-Oct-2019 05:15                3922
swis2-VHDL20_DWEG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3894
swis2-VHDL20_DWEG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3811
swis2-VHDL20_DWEG_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:45                3765
swis2-VHDL20_DWEH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3611
swis2-VHDL20_DWEH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3797
swis2-VHDL20_DWEH_200400-1910200400-dsw--0-ia5     20-Oct-2019 05:15                3781
swis2-VHDL20_DWEH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4553
swis2-VHDL20_DWEH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                3812
swis2-VHDL20_DWEH_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:45                3792
swis2-VHDL20_DWEH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3757
swis2-VHDL20_DWEH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3914
swis2-VHDL20_DWEH_210400-1910210400-dsw--0-ia5     21-Oct-2019 05:15                3991
swis2-VHDL20_DWEH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                4540
swis2-VHDL20_DWEH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3796
swis2-VHDL20_DWEH_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:45                3776
swis2-VHDL20_DWEI_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                4191
swis2-VHDL20_DWEI_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                4229
swis2-VHDL20_DWEI_200400-1910200400-dsw--0-ia5     20-Oct-2019 05:15                4334
swis2-VHDL20_DWEI_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4337
swis2-VHDL20_DWEI_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                4367
swis2-VHDL20_DWEI_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:45                4416
swis2-VHDL20_DWEI_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                4113
swis2-VHDL20_DWEI_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3991
swis2-VHDL20_DWEI_210400-1910210400-dsw--0-ia5     21-Oct-2019 05:15                4010
swis2-VHDL20_DWEI_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3980
swis2-VHDL20_DWEI_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3877
swis2-VHDL20_DWEI_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:45                3927
swis2-VHDL20_DWHG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3416
swis2-VHDL20_DWHG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3636
swis2-VHDL20_DWHG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                3635
swis2-VHDL20_DWHG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4293
swis2-VHDL20_DWHG_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:45                4290
swis2-VHDL20_DWHG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                4163
swis2-VHDL20_DWHG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                4137
swis2-VHDL20_DWHG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3962
swis2-VHDL20_DWHG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                4008
swis2-VHDL20_DWHG_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:45                3964
swis2-VHDL20_DWHH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                2860
swis2-VHDL20_DWHH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                2736
swis2-VHDL20_DWHH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                2730
swis2-VHDL20_DWHH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3347
swis2-VHDL20_DWHH_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:45                3326
swis2-VHDL20_DWHH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3188
swis2-VHDL20_DWHH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3156
swis2-VHDL20_DWHH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3147
swis2-VHDL20_DWHH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3143
swis2-VHDL20_DWHH_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:45                3353
swis2-VHDL20_DWLG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3333
swis2-VHDL20_DWLG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3544
swis2-VHDL20_DWLG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                3562
swis2-VHDL20_DWLG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3556
swis2-VHDL20_DWLG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                3500
swis2-VHDL20_DWLG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3255
swis2-VHDL20_DWLG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3564
swis2-VHDL20_DWLG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3604
swis2-VHDL20_DWLG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3689
swis2-VHDL20_DWLG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3676
swis2-VHDL20_DWLH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3506
swis2-VHDL20_DWLH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3765
swis2-VHDL20_DWLH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                3727
swis2-VHDL20_DWLH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3726
swis2-VHDL20_DWLH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                3695
swis2-VHDL20_DWLH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3334
swis2-VHDL20_DWLH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3543
swis2-VHDL20_DWLH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3613
swis2-VHDL20_DWLH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3995
swis2-VHDL20_DWLH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3985
swis2-VHDL20_DWLI_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                3493
swis2-VHDL20_DWLI_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                3775
swis2-VHDL20_DWLI_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                3737
swis2-VHDL20_DWLI_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                3736
swis2-VHDL20_DWLI_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                3695
swis2-VHDL20_DWLI_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3332
swis2-VHDL20_DWLI_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3548
swis2-VHDL20_DWLI_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3594
swis2-VHDL20_DWLI_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3687
swis2-VHDL20_DWLI_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                3712
swis2-VHDL20_DWMG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                5618
swis2-VHDL20_DWMG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                5598
swis2-VHDL20_DWMG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                5521
swis2-VHDL20_DWMG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                5420
swis2-VHDL20_DWMG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                5338
swis2-VHDL20_DWMG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                5288
swis2-VHDL20_DWMG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                5347
swis2-VHDL20_DWMG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                5226
swis2-VHDL20_DWMG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                5132
swis2-VHDL20_DWMG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                5331
swis2-VHDL20_DWMO_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                4097
swis2-VHDL20_DWMO_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                4339
swis2-VHDL20_DWMO_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                4211
swis2-VHDL20_DWMO_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4131
swis2-VHDL20_DWMO_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                4000
swis2-VHDL20_DWMO_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3923
swis2-VHDL20_DWMO_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                4137
swis2-VHDL20_DWMO_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                4182
swis2-VHDL20_DWMO_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                4187
swis2-VHDL20_DWMO_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                4203
swis2-VHDL20_DWMP_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                5279
swis2-VHDL20_DWMP_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                5595
swis2-VHDL20_DWMP_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                5581
swis2-VHDL20_DWMP_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                5431
swis2-VHDL20_DWMP_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:45                5375
swis2-VHDL20_DWMP_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                5127
swis2-VHDL20_DWMP_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                5167
swis2-VHDL20_DWMP_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                5022
swis2-VHDL20_DWMP_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                5012
swis2-VHDL20_DWMP_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:45                5185
swis2-VHDL20_DWPG_191730-1910191730-dsw--0-ia5     19-Oct-2019 17:30                3236
swis2-VHDL20_DWPG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                3146
swis2-VHDL20_DWPG_191930-1910191930-dsw--0-ia5     19-Oct-2019 19:30                3145
swis2-VHDL20_DWPG_192030-1910192030-dsw--0-ia5     19-Oct-2019 20:30                3145
swis2-VHDL20_DWPG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                3294
swis2-VHDL20_DWPG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                3186
swis2-VHDL20_DWPG_200530-1910200530-dsw--0-ia5     20-Oct-2019 05:31                3186
swis2-VHDL20_DWPG_200630-1910200630-dsw--0-ia5     20-Oct-2019 06:30                3186
swis2-VHDL20_DWPG_200730-1910200730-dsw--0-ia5     20-Oct-2019 07:30                3186
swis2-VHDL20_DWPG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2904
swis2-VHDL20_DWPG_200930-1910200930-dsw--0-ia5     20-Oct-2019 09:30                2966
swis2-VHDL20_DWPG_201030-1910201030-dsw--0-ia5     20-Oct-2019 10:30                2966
swis2-VHDL20_DWPG_201130-1910201130-dsw--0-ia5     20-Oct-2019 11:30                2930
swis2-VHDL20_DWPG_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                2897
swis2-VHDL20_DWPG_201330-1910201330-dsw--0-ia5     20-Oct-2019 13:30                2934
swis2-VHDL20_DWPG_201430-1910201430-dsw--0-ia5     20-Oct-2019 14:30                2934
swis2-VHDL20_DWPG_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                2925
swis2-VHDL20_DWPG_201630-1910201630-dsw--0-ia5     20-Oct-2019 16:30                2961
swis2-VHDL20_DWPG_201730-1910201730-dsw--0-ia5     20-Oct-2019 17:30                2961
swis2-VHDL20_DWPG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:31                2944
swis2-VHDL20_DWPG_201930-1910201930-dsw--0-ia5     20-Oct-2019 19:30                2943
swis2-VHDL20_DWPG_202030-1910202030-dsw--0-ia5     20-Oct-2019 20:30                2943
swis2-VHDL20_DWPG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                2904
swis2-VHDL20_DWPG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:31                2893
swis2-VHDL20_DWPG_210530-1910210530-dsw--0-ia5     21-Oct-2019 05:30                2965
swis2-VHDL20_DWPG_210630-1910210630-dsw--0-ia5     21-Oct-2019 06:30                2965
swis2-VHDL20_DWPG_210730-1910210730-dsw--0-ia5     21-Oct-2019 07:30                2965
swis2-VHDL20_DWPG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2926
swis2-VHDL20_DWPG_210930-1910210930-dsw--0-ia5     21-Oct-2019 09:30                2988
swis2-VHDL20_DWPG_211030-1910211030-dsw--0-ia5     21-Oct-2019 10:31                2988
swis2-VHDL20_DWPG_211130-1910211130-dsw--0-ia5     21-Oct-2019 11:30                2933
swis2-VHDL20_DWPG_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                2886
swis2-VHDL20_DWPG_211330-1910211330-dsw--0-ia5     21-Oct-2019 13:30                2915
swis2-VHDL20_DWPG_211430-1910211430-dsw--0-ia5     21-Oct-2019 14:30                2915
swis2-VHDL20_DWPG_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                2952
swis2-VHDL20_DWPG_211630-1910211630-dsw--0-ia5     21-Oct-2019 16:30                2981
swis2-VHDL20_DWPH_191730-1910191730-dsw--0-ia5     19-Oct-2019 17:30                3230
swis2-VHDL20_DWPH_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:30                2998
swis2-VHDL20_DWPH_191930-1910191930-dsw--0-ia5     19-Oct-2019 19:30                2998
swis2-VHDL20_DWPH_192030-1910192030-dsw--0-ia5     19-Oct-2019 20:30                2998
swis2-VHDL20_DWPH_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:30                3178
swis2-VHDL20_DWPH_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:30                2932
swis2-VHDL20_DWPH_200530-1910200530-dsw--0-ia5     20-Oct-2019 05:30                2932
swis2-VHDL20_DWPH_200630-1910200630-dsw--0-ia5     20-Oct-2019 06:30                2932
swis2-VHDL20_DWPH_200730-1910200730-dsw--0-ia5     20-Oct-2019 07:30                2932
swis2-VHDL20_DWPH_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:30                2979
swis2-VHDL20_DWPH_200930-1910200930-dsw--0-ia5     20-Oct-2019 09:30                3042
swis2-VHDL20_DWPH_201030-1910201030-dsw--0-ia5     20-Oct-2019 10:30                3042
swis2-VHDL20_DWPH_201130-1910201130-dsw--0-ia5     20-Oct-2019 11:30                3024
swis2-VHDL20_DWPH_201300-1910201300-dsw--0-ia5     20-Oct-2019 12:30                3060
swis2-VHDL20_DWPH_201330-1910201330-dsw--0-ia5     20-Oct-2019 13:30                3075
swis2-VHDL20_DWPH_201430-1910201430-dsw--0-ia5     20-Oct-2019 14:30                3075
swis2-VHDL20_DWPH_201500-1910201500-dsw--0-ia5     20-Oct-2019 15:30                2979
swis2-VHDL20_DWPH_201630-1910201630-dsw--0-ia5     20-Oct-2019 16:30                2979
swis2-VHDL20_DWPH_201730-1910201730-dsw--0-ia5     20-Oct-2019 17:30                2979
swis2-VHDL20_DWPH_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:30                2796
swis2-VHDL20_DWPH_201930-1910201930-dsw--0-ia5     20-Oct-2019 19:30                2796
swis2-VHDL20_DWPH_202030-1910202030-dsw--0-ia5     20-Oct-2019 20:30                2796
swis2-VHDL20_DWPH_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:30                3057
swis2-VHDL20_DWPH_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:30                3065
swis2-VHDL20_DWPH_210530-1910210530-dsw--0-ia5     21-Oct-2019 05:30                3065
swis2-VHDL20_DWPH_210630-1910210630-dsw--0-ia5     21-Oct-2019 06:30                3065
swis2-VHDL20_DWPH_210730-1910210730-dsw--0-ia5     21-Oct-2019 07:30                3065
swis2-VHDL20_DWPH_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:30                2922
swis2-VHDL20_DWPH_210930-1910210930-dsw--0-ia5     21-Oct-2019 09:30                2985
swis2-VHDL20_DWPH_211030-1910211030-dsw--0-ia5     21-Oct-2019 10:30                3048
swis2-VHDL20_DWPH_211130-1910211130-dsw--0-ia5     21-Oct-2019 11:30                3062
swis2-VHDL20_DWPH_211300-1910211300-dsw--0-ia5     21-Oct-2019 12:30                3005
swis2-VHDL20_DWPH_211330-1910211330-dsw--0-ia5     21-Oct-2019 13:30                3005
swis2-VHDL20_DWPH_211430-1910211430-dsw--0-ia5     21-Oct-2019 14:30                3005
swis2-VHDL20_DWPH_211500-1910211500-dsw--0-ia5     21-Oct-2019 15:30                2905
swis2-VHDL20_DWPH_211630-1910211630-dsw--0-ia5     21-Oct-2019 16:30                2905
swis2-VHDL20_DWSG_191800-1910191800-dsw--0-ia5     19-Oct-2019 18:45                4144
swis2-VHDL20_DWSG_200200-1910200200-dsw--0-ia5     20-Oct-2019 02:45                4202
swis2-VHDL20_DWSG_200400-1910200400-dsw--0-ia5     20-Oct-2019 04:45                4139
swis2-VHDL20_DWSG_200800-1910200800-dsw--0-ia5     20-Oct-2019 08:45                4080
swis2-VHDL20_DWSG_201300-1910201300-dsw--0-ia5     20-Oct-2019 13:45                4185
swis2-VHDL20_DWSG_201800-1910201800-dsw--0-ia5     20-Oct-2019 18:45                3838
swis2-VHDL20_DWSG_210200-1910210200-dsw--0-ia5     21-Oct-2019 02:45                3780
swis2-VHDL20_DWSG_210400-1910210400-dsw--0-ia5     21-Oct-2019 04:45                3882
swis2-VHDL20_DWSG_210800-1910210800-dsw--0-ia5     21-Oct-2019 08:45                3784
swis2-VHDL20_DWSG_211300-1910211300-dsw--0-ia5     21-Oct-2019 13:45                3849