Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_190600                                 19-Oct-2020 07:28                2631
FPDL13_DWMZ_200600                                 20-Oct-2020 08:10                6816
SXDL31_DWAV_190800                                 19-Oct-2020 08:00                8029
SXDL31_DWAV_191800                                 19-Oct-2020 16:53               12288
SXDL31_DWAV_200800                                 20-Oct-2020 07:36               10412
SXDL31_DWAV_201800                                 20-Oct-2020 16:49                8376
SXDL33_DWAV_190000                                 19-Oct-2020 09:59               13211
SXDL33_DWAV_200000                                 20-Oct-2020 10:03               15980
ber01-FWDL39_DWMS_191230-2010191230-dsw--0-ia5     19-Oct-2020 12:24                 992
ber01-FWDL39_DWMS_201230-2010201230-dsw--0-ia5     20-Oct-2020 11:21                 947
ber01-VHDL13_DWEH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:28                2589
ber01-VHDL13_DWEH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:58                2505
ber01-VHDL13_DWEH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:28                2487
ber01-VHDL13_DWEH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:28                2527
ber01-VHDL13_DWEH_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:28                2502
ber01-VHDL13_DWEH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:28                2388
ber01-VHDL13_DWEH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:28                2415
ber01-VHDL13_DWEH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:58                2391
ber01-VHDL13_DWEH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:28                2605
ber01-VHDL13_DWEH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:28                2456
ber01-VHDL13_DWEH_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:28                2371
ber01-VHDL13_DWEH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:28                2235
ber01-VHDL13_DWHG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2427
ber01-VHDL13_DWHG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2432
ber01-VHDL13_DWHG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2576
ber01-VHDL13_DWHG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2531
ber01-VHDL13_DWHG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2183
ber01-VHDL13_DWHG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2366
ber01-VHDL13_DWHG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2323
ber01-VHDL13_DWHG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2549
ber01-VHDL13_DWHG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2632
ber01-VHDL13_DWHG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2299
ber01-VHDL13_DWHH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2251
ber01-VHDL13_DWHH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2270
ber01-VHDL13_DWHH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2262
ber01-VHDL13_DWHH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2234
ber01-VHDL13_DWHH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                1922
ber01-VHDL13_DWHH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2264
ber01-VHDL13_DWHH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2249
ber01-VHDL13_DWHH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2426
ber01-VHDL13_DWHH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2571
ber01-VHDL13_DWHH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2402
ber01-VHDL13_DWLG_190033-2010190033-dsw--0-ia5     19-Oct-2020 00:33                2245
ber01-VHDL13_DWLG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2423
ber01-VHDL13_DWLG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2347
ber01-VHDL13_DWLG_190533-2010190533-dsw--0-ia5     19-Oct-2020 05:33                2350
ber01-VHDL13_DWLG_190633-2010190633-dsw--0-ia5     19-Oct-2020 06:33                2350
ber01-VHDL13_DWLG_190733-2010190733-dsw--0-ia5     19-Oct-2020 07:33                2350
ber01-VHDL13_DWLG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2411
ber01-VHDL13_DWLG_190933-2010190933-dsw--0-ia5     19-Oct-2020 09:33                2417
ber01-VHDL13_DWLG_191033-2010191033-dsw--0-ia5     19-Oct-2020 10:33                2417
ber01-VHDL13_DWLG_191133-2010191133-dsw--0-ia5     19-Oct-2020 11:33                2540
ber01-VHDL13_DWLG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2528
ber01-VHDL13_DWLG_191333-2010191333-dsw--0-ia5     19-Oct-2020 13:33                2531
ber01-VHDL13_DWLG_191433-2010191433-dsw--0-ia5     19-Oct-2020 14:33                2428
ber01-VHDL13_DWLG_191533-2010191533-dsw--0-ia5     19-Oct-2020 15:33                2428
ber01-VHDL13_DWLG_191633-2010191633-dsw--0-ia5     19-Oct-2020 16:33                2428
ber01-VHDL13_DWLG_191733-2010191733-dsw--0-ia5     19-Oct-2020 17:33                2428
ber01-VHDL13_DWLG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2422
ber01-VHDL13_DWLG_191933-2010191933-dsw--0-ia5     19-Oct-2020 19:33                2237
ber01-VHDL13_DWLG_192033-2010192033-dsw--0-ia5     19-Oct-2020 20:33                2237
ber01-VHDL13_DWLG_200033-2010200033-dsw--0-ia5     20-Oct-2020 00:33                2283
ber01-VHDL13_DWLG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2331
ber01-VHDL13_DWLG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2367
ber01-VHDL13_DWLG_200533-2010200533-dsw--0-ia5     20-Oct-2020 05:33                2370
ber01-VHDL13_DWLG_200633-2010200633-dsw--0-ia5     20-Oct-2020 06:33                2304
ber01-VHDL13_DWLG_200733-2010200733-dsw--0-ia5     20-Oct-2020 07:33                2301
ber01-VHDL13_DWLG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2305
ber01-VHDL13_DWLG_200933-2010200933-dsw--0-ia5     20-Oct-2020 09:33                2311
ber01-VHDL13_DWLG_201033-2010201033-dsw--0-ia5     20-Oct-2020 10:33                2325
ber01-VHDL13_DWLG_201133-2010201133-dsw--0-ia5     20-Oct-2020 11:33                2325
ber01-VHDL13_DWLG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2309
ber01-VHDL13_DWLG_201333-2010201333-dsw--0-ia5     20-Oct-2020 13:33                2312
ber01-VHDL13_DWLG_201433-2010201433-dsw--0-ia5     20-Oct-2020 14:33                2285
ber01-VHDL13_DWLG_201533-2010201533-dsw--0-ia5     20-Oct-2020 15:33                2285
ber01-VHDL13_DWLG_201633-2010201633-dsw--0-ia5     20-Oct-2020 16:33                2285
ber01-VHDL13_DWLG_201733-2010201733-dsw--0-ia5     20-Oct-2020 17:33                2096
ber01-VHDL13_DWLG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2097
ber01-VHDL13_DWLG_201933-2010201933-dsw--0-ia5     20-Oct-2020 19:33                2100
ber01-VHDL13_DWLG_202033-2010202033-dsw--0-ia5     20-Oct-2020 20:33                2100
ber01-VHDL13_DWLH_190033-2010190033-dsw--0-ia5     19-Oct-2020 00:33                2138
ber01-VHDL13_DWLH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2457
ber01-VHDL13_DWLH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2398
ber01-VHDL13_DWLH_190533-2010190533-dsw--0-ia5     19-Oct-2020 05:33                2404
ber01-VHDL13_DWLH_190633-2010190633-dsw--0-ia5     19-Oct-2020 06:33                2404
ber01-VHDL13_DWLH_190733-2010190733-dsw--0-ia5     19-Oct-2020 07:33                2404
ber01-VHDL13_DWLH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2415
ber01-VHDL13_DWLH_190933-2010190933-dsw--0-ia5     19-Oct-2020 09:33                2421
ber01-VHDL13_DWLH_191033-2010191033-dsw--0-ia5     19-Oct-2020 10:33                2421
ber01-VHDL13_DWLH_191133-2010191133-dsw--0-ia5     19-Oct-2020 11:33                2751
ber01-VHDL13_DWLH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2645
ber01-VHDL13_DWLH_191333-2010191333-dsw--0-ia5     19-Oct-2020 13:33                2651
ber01-VHDL13_DWLH_191433-2010191433-dsw--0-ia5     19-Oct-2020 14:33                2636
ber01-VHDL13_DWLH_191533-2010191533-dsw--0-ia5     19-Oct-2020 15:33                2636
ber01-VHDL13_DWLH_191633-2010191633-dsw--0-ia5     19-Oct-2020 16:33                2636
ber01-VHDL13_DWLH_191733-2010191733-dsw--0-ia5     19-Oct-2020 17:33                2619
ber01-VHDL13_DWLH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2403
ber01-VHDL13_DWLH_191933-2010191933-dsw--0-ia5     19-Oct-2020 19:33                2412
ber01-VHDL13_DWLH_192033-2010192033-dsw--0-ia5     19-Oct-2020 20:33                2412
ber01-VHDL13_DWLH_200033-2010200033-dsw--0-ia5     20-Oct-2020 00:33                2403
ber01-VHDL13_DWLH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2570
ber01-VHDL13_DWLH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2597
ber01-VHDL13_DWLH_200533-2010200533-dsw--0-ia5     20-Oct-2020 05:33                2603
ber01-VHDL13_DWLH_200633-2010200633-dsw--0-ia5     20-Oct-2020 06:33                2710
ber01-VHDL13_DWLH_200733-2010200733-dsw--0-ia5     20-Oct-2020 07:33                2696
ber01-VHDL13_DWLH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2691
ber01-VHDL13_DWLH_200933-2010200933-dsw--0-ia5     20-Oct-2020 09:33                2697
ber01-VHDL13_DWLH_201033-2010201033-dsw--0-ia5     20-Oct-2020 10:33                2656
ber01-VHDL13_DWLH_201133-2010201133-dsw--0-ia5     20-Oct-2020 11:33                2656
ber01-VHDL13_DWLH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2631
ber01-VHDL13_DWLH_201333-2010201333-dsw--0-ia5     20-Oct-2020 13:33                2637
ber01-VHDL13_DWLH_201433-2010201433-dsw--0-ia5     20-Oct-2020 14:33                2604
ber01-VHDL13_DWLH_201533-2010201533-dsw--0-ia5     20-Oct-2020 15:33                2604
ber01-VHDL13_DWLH_201633-2010201633-dsw--0-ia5     20-Oct-2020 16:33                2586
ber01-VHDL13_DWLH_201733-2010201733-dsw--0-ia5     20-Oct-2020 17:33                2319
ber01-VHDL13_DWLH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2255
ber01-VHDL13_DWLH_201933-2010201933-dsw--0-ia5     20-Oct-2020 19:33                2261
ber01-VHDL13_DWLH_202033-2010202033-dsw--0-ia5     20-Oct-2020 20:33                2261
ber01-VHDL13_DWLI_190033-2010190033-dsw--0-ia5     19-Oct-2020 00:33                2211
ber01-VHDL13_DWLI_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2371
ber01-VHDL13_DWLI_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2295
ber01-VHDL13_DWLI_190533-2010190533-dsw--0-ia5     19-Oct-2020 05:33                2298
ber01-VHDL13_DWLI_190633-2010190633-dsw--0-ia5     19-Oct-2020 06:33                2298
ber01-VHDL13_DWLI_190733-2010190733-dsw--0-ia5     19-Oct-2020 07:33                2298
ber01-VHDL13_DWLI_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2341
ber01-VHDL13_DWLI_190933-2010190933-dsw--0-ia5     19-Oct-2020 09:33                2344
ber01-VHDL13_DWLI_191033-2010191033-dsw--0-ia5     19-Oct-2020 10:33                2344
ber01-VHDL13_DWLI_191133-2010191133-dsw--0-ia5     19-Oct-2020 11:33                2352
ber01-VHDL13_DWLI_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2476
ber01-VHDL13_DWLI_191333-2010191333-dsw--0-ia5     19-Oct-2020 13:33                2479
ber01-VHDL13_DWLI_191433-2010191433-dsw--0-ia5     19-Oct-2020 14:33                2479
ber01-VHDL13_DWLI_191533-2010191533-dsw--0-ia5     19-Oct-2020 15:33                2479
ber01-VHDL13_DWLI_191633-2010191633-dsw--0-ia5     19-Oct-2020 16:33                2479
ber01-VHDL13_DWLI_191733-2010191733-dsw--0-ia5     19-Oct-2020 17:33                2472
ber01-VHDL13_DWLI_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2208
ber01-VHDL13_DWLI_191933-2010191933-dsw--0-ia5     19-Oct-2020 19:33                2214
ber01-VHDL13_DWLI_192033-2010192033-dsw--0-ia5     19-Oct-2020 20:33                2214
ber01-VHDL13_DWLI_200033-2010200033-dsw--0-ia5     20-Oct-2020 00:33                2269
ber01-VHDL13_DWLI_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2253
ber01-VHDL13_DWLI_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2298
ber01-VHDL13_DWLI_200533-2010200533-dsw--0-ia5     20-Oct-2020 05:33                2301
ber01-VHDL13_DWLI_200633-2010200633-dsw--0-ia5     20-Oct-2020 06:33                2387
ber01-VHDL13_DWLI_200733-2010200733-dsw--0-ia5     20-Oct-2020 07:33                2373
ber01-VHDL13_DWLI_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2370
ber01-VHDL13_DWLI_200933-2010200933-dsw--0-ia5     20-Oct-2020 09:33                2373
ber01-VHDL13_DWLI_201033-2010201033-dsw--0-ia5     20-Oct-2020 10:33                2341
ber01-VHDL13_DWLI_201133-2010201133-dsw--0-ia5     20-Oct-2020 11:33                2341
ber01-VHDL13_DWLI_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2333
ber01-VHDL13_DWLI_201333-2010201333-dsw--0-ia5     20-Oct-2020 13:33                2336
ber01-VHDL13_DWLI_201433-2010201433-dsw--0-ia5     20-Oct-2020 14:33                2328
ber01-VHDL13_DWLI_201533-2010201533-dsw--0-ia5     20-Oct-2020 15:33                2328
ber01-VHDL13_DWLI_201633-2010201633-dsw--0-ia5     20-Oct-2020 16:33                2328
ber01-VHDL13_DWLI_201733-2010201733-dsw--0-ia5     20-Oct-2020 17:33                2056
ber01-VHDL13_DWLI_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2043
ber01-VHDL13_DWLI_201933-2010201933-dsw--0-ia5     20-Oct-2020 19:33                2046
ber01-VHDL13_DWLI_202033-2010202033-dsw--0-ia5     20-Oct-2020 20:33                2046
ber01-VHDL13_DWMG_182300-2010182300-dsw--0-ia5     18-Oct-2020 23:30                2674
ber01-VHDL13_DWMG_190000-2010190000-dsw--0-ia5     19-Oct-2020 00:30                2674
ber01-VHDL13_DWMG_190100-2010190100-dsw--0-ia5     19-Oct-2020 01:30                2674
ber01-VHDL13_DWMG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2674
ber01-VHDL13_DWMG_190300-2010190300-dsw--0-ia5     19-Oct-2020 03:30                2674
ber01-VHDL13_DWMG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2532
ber01-VHDL13_DWMG_190500-2010190500-dsw--0-ia5     19-Oct-2020 05:30                2532
ber01-VHDL13_DWMG_190600-2010190600-dsw--0-ia5     19-Oct-2020 06:30                2532
ber01-VHDL13_DWMG_190700-2010190700-dsw--0-ia5     19-Oct-2020 07:30                2811
ber01-VHDL13_DWMG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2982
ber01-VHDL13_DWMG_190900-2010190900-dsw--0-ia5     19-Oct-2020 09:30                2982
ber01-VHDL13_DWMG_191000-2010191000-dsw--0-ia5     19-Oct-2020 10:30                2945
ber01-VHDL13_DWMG_191100-2010191100-dsw--0-ia5     19-Oct-2020 11:30                2966
ber01-VHDL13_DWMG_191200-2010191200-dsw--0-ia5     19-Oct-2020 12:30                2966
ber01-VHDL13_DWMG_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                2821
ber01-VHDL13_DWMG_191400-2010191400-dsw--0-ia5     19-Oct-2020 14:30                2821
ber01-VHDL13_DWMG_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2821
ber01-VHDL13_DWMG_191600-2010191600-dsw--0-ia5     19-Oct-2020 16:30                2558
ber01-VHDL13_DWMG_191700-2010191700-dsw--0-ia5     19-Oct-2020 17:30                2558
ber01-VHDL13_DWMG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                3132
ber01-VHDL13_DWMG_191900-2010191900-dsw--0-ia5     19-Oct-2020 19:30                3132
ber01-VHDL13_DWMG_192000-2010192000-dsw--0-ia5     19-Oct-2020 20:30                3132
ber01-VHDL13_DWMG_192100-2010192100-dsw--0-ia5     19-Oct-2020 21:30                3132
ber01-VHDL13_DWMG_192200-2010192200-dsw--0-ia5     19-Oct-2020 22:30                3168
ber01-VHDL13_DWMG_192300-2010192300-dsw--0-ia5     19-Oct-2020 23:30                3168
ber01-VHDL13_DWMG_200000-2010200000-dsw--0-ia5     20-Oct-2020 00:30                3168
ber01-VHDL13_DWMG_200100-2010200100-dsw--0-ia5     20-Oct-2020 01:30                3168
ber01-VHDL13_DWMG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                3168
ber01-VHDL13_DWMG_200300-2010200300-dsw--0-ia5     20-Oct-2020 03:30                3168
ber01-VHDL13_DWMG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                3112
ber01-VHDL13_DWMG_200500-2010200500-dsw--0-ia5     20-Oct-2020 05:30                3112
ber01-VHDL13_DWMG_200600-2010200600-dsw--0-ia5     20-Oct-2020 06:30                3112
ber01-VHDL13_DWMG_200700-2010200700-dsw--0-ia5     20-Oct-2020 07:30                3112
ber01-VHDL13_DWMG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                3180
ber01-VHDL13_DWMG_200900-2010200900-dsw--0-ia5     20-Oct-2020 09:30                3180
ber01-VHDL13_DWMG_201000-2010201000-dsw--0-ia5     20-Oct-2020 10:30                3251
ber01-VHDL13_DWMG_201100-2010201100-dsw--0-ia5     20-Oct-2020 11:30                3251
ber01-VHDL13_DWMG_201200-2010201200-dsw--0-ia5     20-Oct-2020 12:30                3251
ber01-VHDL13_DWMG_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                3053
ber01-VHDL13_DWMG_201400-2010201400-dsw--0-ia5     20-Oct-2020 14:30                3053
ber01-VHDL13_DWMG_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                3053
ber01-VHDL13_DWMG_201600-2010201600-dsw--0-ia5     20-Oct-2020 16:30                2843
ber01-VHDL13_DWMG_201700-2010201700-dsw--0-ia5     20-Oct-2020 17:30                2843
ber01-VHDL13_DWMG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2948
ber01-VHDL13_DWMG_201900-2010201900-dsw--0-ia5     20-Oct-2020 19:30                2948
ber01-VHDL13_DWMG_202000-2010202000-dsw--0-ia5     20-Oct-2020 20:30                2948
ber01-VHDL13_DWMG_202100-2010202100-dsw--0-ia5     20-Oct-2020 21:30                2948
ber01-VHDL13_DWMG_202200-2010202200-dsw--0-ia5     20-Oct-2020 22:30                3146
ber01-VHDL13_DWMO_182300-2010182300-dsw--0-ia5     18-Oct-2020 23:30                2319
ber01-VHDL13_DWMO_190000-2010190000-dsw--0-ia5     19-Oct-2020 00:30                2319
ber01-VHDL13_DWMO_190100-2010190100-dsw--0-ia5     19-Oct-2020 01:30                2319
ber01-VHDL13_DWMO_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2319
ber01-VHDL13_DWMO_190300-2010190300-dsw--0-ia5     19-Oct-2020 03:30                2319
ber01-VHDL13_DWMO_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2131
ber01-VHDL13_DWMO_190500-2010190500-dsw--0-ia5     19-Oct-2020 05:30                2131
ber01-VHDL13_DWMO_190600-2010190600-dsw--0-ia5     19-Oct-2020 06:30                2131
ber01-VHDL13_DWMO_190700-2010190700-dsw--0-ia5     19-Oct-2020 07:30                2131
ber01-VHDL13_DWMO_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2906
ber01-VHDL13_DWMO_190900-2010190900-dsw--0-ia5     19-Oct-2020 09:30                2878
ber01-VHDL13_DWMO_191000-2010191000-dsw--0-ia5     19-Oct-2020 10:30                2878
ber01-VHDL13_DWMO_191100-2010191100-dsw--0-ia5     19-Oct-2020 11:30                2798
ber01-VHDL13_DWMO_191200-2010191200-dsw--0-ia5     19-Oct-2020 12:30                2798
ber01-VHDL13_DWMO_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                2673
ber01-VHDL13_DWMO_191400-2010191400-dsw--0-ia5     19-Oct-2020 14:30                2673
ber01-VHDL13_DWMO_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2673
ber01-VHDL13_DWMO_191600-2010191600-dsw--0-ia5     19-Oct-2020 16:30                2450
ber01-VHDL13_DWMO_191700-2010191700-dsw--0-ia5     19-Oct-2020 17:30                2450
ber01-VHDL13_DWMO_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2450
ber01-VHDL13_DWMO_191900-2010191900-dsw--0-ia5     19-Oct-2020 19:30                2607
ber01-VHDL13_DWMO_192000-2010192000-dsw--0-ia5     19-Oct-2020 20:30                2607
ber01-VHDL13_DWMO_192100-2010192100-dsw--0-ia5     19-Oct-2020 21:30                2607
ber01-VHDL13_DWMO_192200-2010192200-dsw--0-ia5     19-Oct-2020 22:30                2597
ber01-VHDL13_DWMO_192300-2010192300-dsw--0-ia5     19-Oct-2020 23:30                2597
ber01-VHDL13_DWMO_200000-2010200000-dsw--0-ia5     20-Oct-2020 00:30                2597
ber01-VHDL13_DWMO_200100-2010200100-dsw--0-ia5     20-Oct-2020 01:30                2597
ber01-VHDL13_DWMO_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2597
ber01-VHDL13_DWMO_200300-2010200300-dsw--0-ia5     20-Oct-2020 03:30                2597
ber01-VHDL13_DWMO_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2532
ber01-VHDL13_DWMO_200500-2010200500-dsw--0-ia5     20-Oct-2020 05:30                2532
ber01-VHDL13_DWMO_200600-2010200600-dsw--0-ia5     20-Oct-2020 06:30                2532
ber01-VHDL13_DWMO_200700-2010200700-dsw--0-ia5     20-Oct-2020 07:30                2532
ber01-VHDL13_DWMO_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2720
ber01-VHDL13_DWMO_200900-2010200900-dsw--0-ia5     20-Oct-2020 09:30                2692
ber01-VHDL13_DWMO_201000-2010201000-dsw--0-ia5     20-Oct-2020 10:30                2772
ber01-VHDL13_DWMO_201100-2010201100-dsw--0-ia5     20-Oct-2020 11:30                2772
ber01-VHDL13_DWMO_201200-2010201200-dsw--0-ia5     20-Oct-2020 12:30                2772
ber01-VHDL13_DWMO_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                2772
ber01-VHDL13_DWMO_201400-2010201400-dsw--0-ia5     20-Oct-2020 14:30                2534
ber01-VHDL13_DWMO_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                2534
ber01-VHDL13_DWMO_201600-2010201600-dsw--0-ia5     20-Oct-2020 16:30                2343
ber01-VHDL13_DWMO_201700-2010201700-dsw--0-ia5     20-Oct-2020 17:30                2343
ber01-VHDL13_DWMO_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2401
ber01-VHDL13_DWMO_201900-2010201900-dsw--0-ia5     20-Oct-2020 19:30                2401
ber01-VHDL13_DWMO_202000-2010202000-dsw--0-ia5     20-Oct-2020 20:30                2401
ber01-VHDL13_DWMO_202100-2010202100-dsw--0-ia5     20-Oct-2020 21:30                2401
ber01-VHDL13_DWMO_202200-2010202200-dsw--0-ia5     20-Oct-2020 22:30                2730
ber01-VHDL13_DWMP_182300-2010182300-dsw--0-ia5     18-Oct-2020 23:30                2781
ber01-VHDL13_DWMP_190000-2010190000-dsw--0-ia5     19-Oct-2020 00:30                2781
ber01-VHDL13_DWMP_190100-2010190100-dsw--0-ia5     19-Oct-2020 01:30                2781
ber01-VHDL13_DWMP_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2781
ber01-VHDL13_DWMP_190300-2010190300-dsw--0-ia5     19-Oct-2020 03:30                2781
ber01-VHDL13_DWMP_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2619
ber01-VHDL13_DWMP_190500-2010190500-dsw--0-ia5     19-Oct-2020 05:30                2619
ber01-VHDL13_DWMP_190600-2010190600-dsw--0-ia5     19-Oct-2020 06:30                2619
ber01-VHDL13_DWMP_190700-2010190700-dsw--0-ia5     19-Oct-2020 07:30                2619
ber01-VHDL13_DWMP_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2619
ber01-VHDL13_DWMP_190900-2010190900-dsw--0-ia5     19-Oct-2020 09:30                3004
ber01-VHDL13_DWMP_191000-2010191000-dsw--0-ia5     19-Oct-2020 10:30                3004
ber01-VHDL13_DWMP_191100-2010191100-dsw--0-ia5     19-Oct-2020 11:30                3039
ber01-VHDL13_DWMP_191200-2010191200-dsw--0-ia5     19-Oct-2020 12:30                3039
ber01-VHDL13_DWMP_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                2903
ber01-VHDL13_DWMP_191400-2010191400-dsw--0-ia5     19-Oct-2020 14:30                2836
ber01-VHDL13_DWMP_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2836
ber01-VHDL13_DWMP_191600-2010191600-dsw--0-ia5     19-Oct-2020 16:30                2836
ber01-VHDL13_DWMP_191700-2010191700-dsw--0-ia5     19-Oct-2020 17:30                2836
ber01-VHDL13_DWMP_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2836
ber01-VHDL13_DWMP_191900-2010191900-dsw--0-ia5     19-Oct-2020 19:30                2970
ber01-VHDL13_DWMP_192000-2010192000-dsw--0-ia5     19-Oct-2020 20:30                2970
ber01-VHDL13_DWMP_192100-2010192100-dsw--0-ia5     19-Oct-2020 21:30                2970
ber01-VHDL13_DWMP_192200-2010192200-dsw--0-ia5     19-Oct-2020 22:30                3160
ber01-VHDL13_DWMP_192300-2010192300-dsw--0-ia5     19-Oct-2020 23:30                3160
ber01-VHDL13_DWMP_200000-2010200000-dsw--0-ia5     20-Oct-2020 00:30                3160
ber01-VHDL13_DWMP_200100-2010200100-dsw--0-ia5     20-Oct-2020 01:30                3160
ber01-VHDL13_DWMP_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                3160
ber01-VHDL13_DWMP_200300-2010200300-dsw--0-ia5     20-Oct-2020 03:30                3160
ber01-VHDL13_DWMP_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                3148
ber01-VHDL13_DWMP_200500-2010200500-dsw--0-ia5     20-Oct-2020 05:30                3148
ber01-VHDL13_DWMP_200600-2010200600-dsw--0-ia5     20-Oct-2020 06:30                3148
ber01-VHDL13_DWMP_200700-2010200700-dsw--0-ia5     20-Oct-2020 07:30                3148
ber01-VHDL13_DWMP_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                3148
ber01-VHDL13_DWMP_200900-2010200900-dsw--0-ia5     20-Oct-2020 09:30                3168
ber01-VHDL13_DWMP_201000-2010201000-dsw--0-ia5     20-Oct-2020 10:30                3231
ber01-VHDL13_DWMP_201100-2010201100-dsw--0-ia5     20-Oct-2020 11:30                3231
ber01-VHDL13_DWMP_201200-2010201200-dsw--0-ia5     20-Oct-2020 12:30                3231
ber01-VHDL13_DWMP_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                3031
ber01-VHDL13_DWMP_201400-2010201400-dsw--0-ia5     20-Oct-2020 14:30                3031
ber01-VHDL13_DWMP_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                3031
ber01-VHDL13_DWMP_201600-2010201600-dsw--0-ia5     20-Oct-2020 16:30                2835
ber01-VHDL13_DWMP_201700-2010201700-dsw--0-ia5     20-Oct-2020 17:30                2835
ber01-VHDL13_DWMP_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2999
ber01-VHDL13_DWMP_201900-2010201900-dsw--0-ia5     20-Oct-2020 19:30                2999
ber01-VHDL13_DWMP_202000-2010202000-dsw--0-ia5     20-Oct-2020 20:30                2999
ber01-VHDL13_DWMP_202100-2010202100-dsw--0-ia5     20-Oct-2020 21:30                2999
ber01-VHDL13_DWMP_202200-2010202200-dsw--0-ia5     20-Oct-2020 22:30                3122
ber01-VHDL13_DWOG_190100-2010190100-dsw--0-ia5     19-Oct-2020 01:45                4100
ber01-VHDL13_DWOG_190300-2010190300-dsw--0-ia5     19-Oct-2020 03:00                4318
ber01-VHDL13_DWOG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:15                4247
ber01-VHDL13_DWOG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:00                4246
ber01-VHDL13_DWOG_191700-2010191700-dsw--0-ia5     19-Oct-2020 17:30                4507
ber01-VHDL13_DWOG_200100-2010200100-dsw--0-ia5     20-Oct-2020 01:45                5277
ber01-VHDL13_DWOG_200300-2010200300-dsw--0-ia5     20-Oct-2020 03:00                5276
ber01-VHDL13_DWOG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:15                5307
ber01-VHDL13_DWOG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:00                4814
ber01-VHDL13_DWOG_201700-2010201700-dsw--0-ia5     20-Oct-2020 17:30                4605
ber01-VHDL13_DWOH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:28                2723
ber01-VHDL13_DWOH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:58                2663
ber01-VHDL13_DWOH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:28                2710
ber01-VHDL13_DWOH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:28                2665
ber01-VHDL13_DWOH_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:28                2542
ber01-VHDL13_DWOH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:28                2432
ber01-VHDL13_DWOH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:28                2424
ber01-VHDL13_DWOH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:58                2399
ber01-VHDL13_DWOH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:28                2645
ber01-VHDL13_DWOH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:28                2451
ber01-VHDL13_DWOH_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:28                2399
ber01-VHDL13_DWOH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:28                2217
ber01-VHDL13_DWOI_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:28                2681
ber01-VHDL13_DWOI_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:58                2666
ber01-VHDL13_DWOI_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:28                2655
ber01-VHDL13_DWOI_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:28                2707
ber01-VHDL13_DWOI_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:28                2652
ber01-VHDL13_DWOI_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:28                2579
ber01-VHDL13_DWOI_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:28                2496
ber01-VHDL13_DWOI_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:58                2489
ber01-VHDL13_DWOI_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:28                2725
ber01-VHDL13_DWOI_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:28                2623
ber01-VHDL13_DWOI_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:28                2610
ber01-VHDL13_DWOI_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:28                2420
ber01-VHDL13_DWON_190009-2010190009-dsw--0-ia5     19-Oct-2020 00:09                4193
ber01-VHDL13_DWON_190055-2010190055-dsw--0-ia5     19-Oct-2020 00:56                4193
ber01-VHDL13_DWON_190253-2010190253-dsw--0-ia5     19-Oct-2020 02:53                4193
ber01-VHDL13_DWON_190522-2010190522-dsw--0-ia5     19-Oct-2020 05:22                4131
ber01-VHDL13_DWON_190707-2010190707-dsw--0-ia5     19-Oct-2020 07:07                4067
ber01-VHDL13_DWON_191030-2010191030-dsw--0-ia5     19-Oct-2020 10:30                4692
ber01-VHDL13_DWON_191125-2010191125-dsw--0-ia5     19-Oct-2020 11:25                4692
ber01-VHDL13_DWON_191432-2010191432-dsw--0-ia5     19-Oct-2020 14:33                4163
ber01-VHDL13_DWON_191711-2010191711-dsw--0-ia5     19-Oct-2020 17:11                4188
ber01-VHDL13_DWON_191936-2010191936-dsw--0-ia5     19-Oct-2020 19:36                4192
ber01-VHDL13_DWON_200013-2010200013-dsw--0-ia5     20-Oct-2020 00:13                4105
ber01-VHDL13_DWON_200104-2010200104-dsw--0-ia5     20-Oct-2020 01:04                4105
ber01-VHDL13_DWON_200241-2010200241-dsw--0-ia5     20-Oct-2020 02:41                4105
ber01-VHDL13_DWON_200527-2010200527-dsw--0-ia5     20-Oct-2020 05:27                3869
ber01-VHDL13_DWON_200710-2010200710-dsw--0-ia5     20-Oct-2020 07:10                4572
ber01-VHDL13_DWON_201117-2010201117-dsw--0-ia5     20-Oct-2020 11:17                4449
ber01-VHDL13_DWON_201454-2010201454-dsw--0-ia5     20-Oct-2020 14:54                4009
ber01-VHDL13_DWON_201621-2010201621-dsw--0-ia5     20-Oct-2020 16:21                4009
ber01-VHDL13_DWON_201722-2010201722-dsw--0-ia5     20-Oct-2020 17:22                3993
ber01-VHDL13_DWON_201726-2010201726-dsw--0-ia5     20-Oct-2020 17:27                3993
ber01-VHDL13_DWON_201743-2010201743-dsw--0-ia5     20-Oct-2020 17:44                3993
ber01-VHDL13_DWON_201744-2010201744-dsw--0-ia5     20-Oct-2020 17:44                3993
ber01-VHDL13_DWPG_190030-2010190030-dsw--0-ia5     19-Oct-2020 00:30                2701
ber01-VHDL13_DWPG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2281
ber01-VHDL13_DWPG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2346
ber01-VHDL13_DWPG_190530-2010190530-dsw--0-ia5     19-Oct-2020 05:30                2344
ber01-VHDL13_DWPG_190630-2010190630-dsw--0-ia5     19-Oct-2020 06:30                2344
ber01-VHDL13_DWPG_190730-2010190730-dsw--0-ia5     19-Oct-2020 07:30                2344
ber01-VHDL13_DWPG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2361
ber01-VHDL13_DWPG_190930-2010190930-dsw--0-ia5     19-Oct-2020 09:30                2360
ber01-VHDL13_DWPG_191030-2010191030-dsw--0-ia5     19-Oct-2020 10:30                2360
ber01-VHDL13_DWPG_191130-2010191130-dsw--0-ia5     19-Oct-2020 11:30                2394
ber01-VHDL13_DWPG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2521
ber01-VHDL13_DWPG_191330-2010191330-dsw--0-ia5     19-Oct-2020 13:30                2526
ber01-VHDL13_DWPG_191430-2010191430-dsw--0-ia5     19-Oct-2020 14:30                2576
ber01-VHDL13_DWPG_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2599
ber01-VHDL13_DWPG_191630-2010191630-dsw--0-ia5     19-Oct-2020 16:30                2629
ber01-VHDL13_DWPG_191730-2010191730-dsw--0-ia5     19-Oct-2020 17:30                2629
ber01-VHDL13_DWPG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2458
ber01-VHDL13_DWPG_191930-2010191930-dsw--0-ia5     19-Oct-2020 19:30                2457
ber01-VHDL13_DWPG_192030-2010192030-dsw--0-ia5     19-Oct-2020 20:30                2457
ber01-VHDL13_DWPG_200030-2010200030-dsw--0-ia5     20-Oct-2020 00:30                2276
ber01-VHDL13_DWPG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2277
ber01-VHDL13_DWPG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2378
ber01-VHDL13_DWPG_200530-2010200530-dsw--0-ia5     20-Oct-2020 05:30                2374
ber01-VHDL13_DWPG_200630-2010200630-dsw--0-ia5     20-Oct-2020 06:30                2374
ber01-VHDL13_DWPG_200730-2010200730-dsw--0-ia5     20-Oct-2020 07:30                2392
ber01-VHDL13_DWPG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2474
ber01-VHDL13_DWPG_200930-2010200930-dsw--0-ia5     20-Oct-2020 09:30                2473
ber01-VHDL13_DWPG_201030-2010201030-dsw--0-ia5     20-Oct-2020 10:30                2473
ber01-VHDL13_DWPG_201130-2010201130-dsw--0-ia5     20-Oct-2020 11:30                2459
ber01-VHDL13_DWPG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2510
ber01-VHDL13_DWPG_201330-2010201330-dsw--0-ia5     20-Oct-2020 13:30                2509
ber01-VHDL13_DWPG_201430-2010201430-dsw--0-ia5     20-Oct-2020 14:30                2509
ber01-VHDL13_DWPG_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                2288
ber01-VHDL13_DWPG_201630-2010201630-dsw--0-ia5     20-Oct-2020 16:30                2287
ber01-VHDL13_DWPG_201730-2010201730-dsw--0-ia5     20-Oct-2020 17:30                2287
ber01-VHDL13_DWPG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2125
ber01-VHDL13_DWPG_201930-2010201930-dsw--0-ia5     20-Oct-2020 19:30                2124
ber01-VHDL13_DWPG_202030-2010202030-dsw--0-ia5     20-Oct-2020 20:30                2124
ber01-VHDL13_DWPH_190030-2010190030-dsw--0-ia5     19-Oct-2020 00:30                2677
ber01-VHDL13_DWPH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2389
ber01-VHDL13_DWPH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2492
ber01-VHDL13_DWPH_190530-2010190530-dsw--0-ia5     19-Oct-2020 05:30                2492
ber01-VHDL13_DWPH_190630-2010190630-dsw--0-ia5     19-Oct-2020 06:30                2492
ber01-VHDL13_DWPH_190730-2010190730-dsw--0-ia5     19-Oct-2020 07:30                2492
ber01-VHDL13_DWPH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2523
ber01-VHDL13_DWPH_190930-2010190930-dsw--0-ia5     19-Oct-2020 09:30                2523
ber01-VHDL13_DWPH_191030-2010191030-dsw--0-ia5     19-Oct-2020 10:30                2523
ber01-VHDL13_DWPH_191130-2010191130-dsw--0-ia5     19-Oct-2020 11:30                2547
ber01-VHDL13_DWPH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2573
ber01-VHDL13_DWPH_191330-2010191330-dsw--0-ia5     19-Oct-2020 13:30                2511
ber01-VHDL13_DWPH_191430-2010191430-dsw--0-ia5     19-Oct-2020 14:30                2500
ber01-VHDL13_DWPH_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2684
ber01-VHDL13_DWPH_191630-2010191630-dsw--0-ia5     19-Oct-2020 16:30                2682
ber01-VHDL13_DWPH_191730-2010191730-dsw--0-ia5     19-Oct-2020 17:30                2682
ber01-VHDL13_DWPH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2485
ber01-VHDL13_DWPH_191930-2010191930-dsw--0-ia5     19-Oct-2020 19:30                2485
ber01-VHDL13_DWPH_192030-2010192030-dsw--0-ia5     19-Oct-2020 20:30                2485
ber01-VHDL13_DWPH_200030-2010200030-dsw--0-ia5     20-Oct-2020 00:30                2273
ber01-VHDL13_DWPH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2273
ber01-VHDL13_DWPH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2328
ber01-VHDL13_DWPH_200530-2010200530-dsw--0-ia5     20-Oct-2020 05:30                2326
ber01-VHDL13_DWPH_200630-2010200630-dsw--0-ia5     20-Oct-2020 06:30                2341
ber01-VHDL13_DWPH_200730-2010200730-dsw--0-ia5     20-Oct-2020 07:30                2341
ber01-VHDL13_DWPH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2287
ber01-VHDL13_DWPH_200930-2010200930-dsw--0-ia5     20-Oct-2020 09:30                2287
ber01-VHDL13_DWPH_201030-2010201030-dsw--0-ia5     20-Oct-2020 10:30                2287
ber01-VHDL13_DWPH_201130-2010201130-dsw--0-ia5     20-Oct-2020 11:30                2290
ber01-VHDL13_DWPH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2300
ber01-VHDL13_DWPH_201330-2010201330-dsw--0-ia5     20-Oct-2020 13:30                2300
ber01-VHDL13_DWPH_201430-2010201430-dsw--0-ia5     20-Oct-2020 14:30                2300
ber01-VHDL13_DWPH_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                2219
ber01-VHDL13_DWPH_201630-2010201630-dsw--0-ia5     20-Oct-2020 16:30                2219
ber01-VHDL13_DWPH_201730-2010201730-dsw--0-ia5     20-Oct-2020 17:30                2219
ber01-VHDL13_DWPH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2381
ber01-VHDL13_DWPH_201930-2010201930-dsw--0-ia5     20-Oct-2020 19:30                2381
ber01-VHDL13_DWPH_202030-2010202030-dsw--0-ia5     20-Oct-2020 20:30                2381
ber01-VHDL13_DWSG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2506
ber01-VHDL13_DWSG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2456
ber01-VHDL13_DWSG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2485
ber01-VHDL13_DWSG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2937
ber01-VHDL13_DWSG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2750
ber01-VHDL13_DWSG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2839
ber01-VHDL13_DWSG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2993
ber01-VHDL13_DWSG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2881
ber01-VHDL13_DWSG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2850
ber01-VHDL13_DWSG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2532
ber01-VHDL13_DWSN_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                1642
ber01-VHDL13_DWSN_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                1656
ber01-VHDL13_DWSN_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                1685
ber01-VHDL13_DWSN_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                1777
ber01-VHDL13_DWSN_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                1605
ber01-VHDL13_DWSN_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                1710
ber01-VHDL13_DWSN_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                1835
ber01-VHDL13_DWSN_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                1733
ber01-VHDL13_DWSN_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                1718
ber01-VHDL13_DWSN_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                1539
ber01-VHDL13_DWSO_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2253
ber01-VHDL13_DWSO_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2189
ber01-VHDL13_DWSO_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2218
ber01-VHDL13_DWSO_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                2564
ber01-VHDL13_DWSO_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2330
ber01-VHDL13_DWSO_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2470
ber01-VHDL13_DWSO_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2466
ber01-VHDL13_DWSO_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2382
ber01-VHDL13_DWSO_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                2307
ber01-VHDL13_DWSO_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2067
ber01-VHDL13_DWSP_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                1859
ber01-VHDL13_DWSP_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                1816
ber01-VHDL13_DWSP_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                1787
ber01-VHDL13_DWSP_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:30                1941
ber01-VHDL13_DWSP_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                1748
ber01-VHDL13_DWSP_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                1874
ber01-VHDL13_DWSP_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                1982
ber01-VHDL13_DWSP_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                1830
ber01-VHDL13_DWSP_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:30                2026
ber01-VHDL13_DWSP_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                1849
ber01-VHDL17_DWOG_191200-2010191200-dsw--0-ia5     19-Oct-2020 10:56                3752
ber01-VHDL17_DWOG_201200-2010201200-dsw--0-ia5     20-Oct-2020 11:10                2542
ber01-VHDL20_DWHG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2932
ber01-VHDL20_DWHG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2932
ber01-VHDL20_DWHG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3076
ber01-VHDL20_DWHG_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:45                3031
ber01-VHDL20_DWHG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2680
ber01-VHDL20_DWHG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2870
ber01-VHDL20_DWHG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2820
ber01-VHDL20_DWHG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3044
ber01-VHDL20_DWHG_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:45                3128
ber01-VHDL20_DWHG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2797
ber01-VHDL20_DWHH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2701
ber01-VHDL20_DWHH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2715
ber01-VHDL20_DWHH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2707
ber01-VHDL20_DWHH_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:45                2679
ber01-VHDL20_DWHH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2364
ber01-VHDL20_DWHH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2712
ber01-VHDL20_DWHH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2691
ber01-VHDL20_DWHH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                2866
ber01-VHDL20_DWHH_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:45                3012
ber01-VHDL20_DWHH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2844
gts01-VHDL12_DWON_190115-2010190145-afsv--68-ia5   19-Oct-2020 01:45                3681
gts01-VHDL12_DWON_190530-2010190530-afsv--89-ia5   19-Oct-2020 05:30                3619
gts01-VHDL12_DWON_190815-2010190815-afsv--64-ia5   19-Oct-2020 08:15                3565
gts01-VHDL12_DWON_191330-2010191230-afsv--21-ia5   19-Oct-2020 12:30                4205
gts01-VHDL12_DWON_191815-2010191745-afsv--55-ia5   19-Oct-2020 17:45                3688
gts01-VHDL12_DWON_200115-2010200145-afsv--82-ia5   20-Oct-2020 01:45                3735
gts01-VHDL12_DWON_200530-2010200530-afsv--09-ia5   20-Oct-2020 05:30                3491
gts01-VHDL12_DWON_200815-2010200815-afsv--83-ia5   20-Oct-2020 08:15                4199
gts01-VHDL12_DWON_201330-2010201230-afsv--20-ia5   20-Oct-2020 12:30                4072
gts01-VHDL12_DWON_201815-2010201745-afsv--78-ia5   20-Oct-2020 17:45                3601
pid-VHDL12_DWEH_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:28                2179
pid-VHDL12_DWEH_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:28                2088
pid-VHDL12_DWHG_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2021
pid-VHDL12_DWHG_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                2024
pid-VHDL12_DWHG_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                2060
pid-VHDL12_DWHG_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                2015
pid-VHDL12_DWHH_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                1917
pid-VHDL12_DWHH_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                1936
pid-VHDL12_DWHH_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                1932
pid-VHDL12_DWHH_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                1917
pid-VHDL12_DWLG_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2085
pid-VHDL12_DWLG_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                2009
pid-VHDL12_DWLG_190800-2010190800-dsw--0-ia5       19-Oct-2020 08:30                2076
pid-VHDL12_DWLG_191300-2010191300-dsw--0-ia5       19-Oct-2020 12:30                2190
pid-VHDL12_DWLG_191800-2010191800-dsw--0-ia5       19-Oct-2020 18:30                2068
pid-VHDL12_DWLG_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                2031
pid-VHDL12_DWLG_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                2066
pid-VHDL12_DWLG_200800-2010200800-dsw--0-ia5       20-Oct-2020 08:30                2007
pid-VHDL12_DWLG_201300-2010201300-dsw--0-ia5       20-Oct-2020 12:30                2008
pid-VHDL12_DWLG_201800-2010201800-dsw--0-ia5       20-Oct-2020 18:30                1796
pid-VHDL12_DWLH_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2115
pid-VHDL12_DWLH_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                2056
pid-VHDL12_DWLH_190800-2010190800-dsw--0-ia5       19-Oct-2020 08:30                2073
pid-VHDL12_DWLH_191300-2010191300-dsw--0-ia5       19-Oct-2020 12:30                2303
pid-VHDL12_DWLH_191800-2010191800-dsw--0-ia5       19-Oct-2020 18:30                2039
pid-VHDL12_DWLH_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                2277
pid-VHDL12_DWLH_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                2303
pid-VHDL12_DWLH_200800-2010200800-dsw--0-ia5       20-Oct-2020 08:30                2397
pid-VHDL12_DWLH_201300-2010201300-dsw--0-ia5       20-Oct-2020 12:30                2337
pid-VHDL12_DWLH_201800-2010201800-dsw--0-ia5       20-Oct-2020 18:30                1961
pid-VHDL12_DWLI_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2001
pid-VHDL12_DWLI_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                1925
pid-VHDL12_DWLI_190800-2010190800-dsw--0-ia5       19-Oct-2020 08:30                1971
pid-VHDL12_DWLI_191300-2010191300-dsw--0-ia5       19-Oct-2020 12:30                2106
pid-VHDL12_DWLI_191800-2010191800-dsw--0-ia5       19-Oct-2020 18:30                1801
pid-VHDL12_DWLI_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                1953
pid-VHDL12_DWLI_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                1997
pid-VHDL12_DWLI_200800-2010200800-dsw--0-ia5       20-Oct-2020 08:30                2069
pid-VHDL12_DWLI_201300-2010201300-dsw--0-ia5       20-Oct-2020 12:30                2032
pid-VHDL12_DWLI_201800-2010201800-dsw--0-ia5       20-Oct-2020 18:30                1742
pid-VHDL12_DWMG_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2225
pid-VHDL12_DWMG_190400-2010190400-dsw--0-ia5       19-Oct-2020 04:30                2083
pid-VHDL12_DWMG_190800-2010190800-dsw--0-ia5       19-Oct-2020 08:30                2504
pid-VHDL12_DWMG_191300-2010191300-dsw--0-ia5       19-Oct-2020 12:30                2488
pid-VHDL12_DWMG_191800-2010191800-dsw--0-ia5       19-Oct-2020 18:30                2594
pid-VHDL12_DWMG_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                2992
pid-VHDL12_DWMG_200400-2010200400-dsw--0-ia5       20-Oct-2020 04:30                2936
pid-VHDL12_DWMG_200800-2010200800-dsw--0-ia5       20-Oct-2020 08:30                2855
pid-VHDL12_DWMG_201300-2010201300-dsw--0-ia5       20-Oct-2020 12:30                2926
pid-VHDL12_DWMG_201800-2010201800-dsw--0-ia5       20-Oct-2020 18:30                2665
pid-VHDL12_DWOG_190100-2010190100-dsw--0-ia5       19-Oct-2020 01:45                3477
pid-VHDL12_DWOG_190300-2010190300-dsw--0-ia5       19-Oct-2020 03:00                3695
pid-VHDL12_DWOG_200100-2010200100-dsw--0-ia5       20-Oct-2020 01:45                4802
pid-VHDL12_DWOG_200300-2010200300-dsw--0-ia5       20-Oct-2020 03:00                4801
pid-VHDL12_DWOH_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:28                2394
pid-VHDL12_DWOH_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:28                2097
pid-VHDL12_DWOI_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:28                2351
pid-VHDL12_DWOI_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:28                2170
pid-VHDL12_DWSG_190200-2010190200-dsw--0-ia5       19-Oct-2020 02:30                2142
pid-VHDL12_DWSG_200200-2010200200-dsw--0-ia5       20-Oct-2020 02:30                2513
swis2-VHDL20_DWEG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                3180
swis2-VHDL20_DWEG_190400-2010190400-dsw--0-ia5     19-Oct-2020 05:15                3170
swis2-VHDL20_DWEG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3171
swis2-VHDL20_DWEG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3172
swis2-VHDL20_DWEG_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:45                3049
swis2-VHDL20_DWEG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2945
swis2-VHDL20_DWEG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2883
swis2-VHDL20_DWEG_200400-2010200400-dsw--0-ia5     20-Oct-2020 05:15                2893
swis2-VHDL20_DWEG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3142
swis2-VHDL20_DWEG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                2948
swis2-VHDL20_DWEG_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:45                2896
swis2-VHDL20_DWEG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2721
swis2-VHDL20_DWEH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                3078
swis2-VHDL20_DWEH_190400-2010190400-dsw--0-ia5     19-Oct-2020 05:15                3017
swis2-VHDL20_DWEH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2956
swis2-VHDL20_DWEH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3045
swis2-VHDL20_DWEH_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:45                3026
swis2-VHDL20_DWEH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2926
swis2-VHDL20_DWEH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2906
swis2-VHDL20_DWEH_200400-2010200400-dsw--0-ia5     20-Oct-2020 05:15                2890
swis2-VHDL20_DWEH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3110
swis2-VHDL20_DWEH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                2961
swis2-VHDL20_DWEH_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:45                2882
swis2-VHDL20_DWEH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2763
swis2-VHDL20_DWEI_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                3139
swis2-VHDL20_DWEI_190400-2010190400-dsw--0-ia5     19-Oct-2020 05:15                3179
swis2-VHDL20_DWEI_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3165
swis2-VHDL20_DWEI_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3223
swis2-VHDL20_DWEI_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:45                3165
swis2-VHDL20_DWEI_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                3092
swis2-VHDL20_DWEI_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2959
swis2-VHDL20_DWEI_200400-2010200400-dsw--0-ia5     20-Oct-2020 05:15                2989
swis2-VHDL20_DWEI_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3222
swis2-VHDL20_DWEI_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                3129
swis2-VHDL20_DWEI_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:45                3113
swis2-VHDL20_DWEI_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2924
swis2-VHDL20_DWHG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2932
swis2-VHDL20_DWHG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2932
swis2-VHDL20_DWHG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3076
swis2-VHDL20_DWHG_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:45                3031
swis2-VHDL20_DWHG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2680
swis2-VHDL20_DWHG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2870
swis2-VHDL20_DWHG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2820
swis2-VHDL20_DWHG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3044
swis2-VHDL20_DWHG_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:45                3128
swis2-VHDL20_DWHG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2797
swis2-VHDL20_DWHH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2701
swis2-VHDL20_DWHH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2715
swis2-VHDL20_DWHH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2707
swis2-VHDL20_DWHH_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:45                2679
swis2-VHDL20_DWHH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2364
swis2-VHDL20_DWHH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2712
swis2-VHDL20_DWHH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2691
swis2-VHDL20_DWHH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                2866
swis2-VHDL20_DWHH_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:45                3012
swis2-VHDL20_DWHH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2844
swis2-VHDL20_DWLG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2848
swis2-VHDL20_DWLG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2775
swis2-VHDL20_DWLG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2842
swis2-VHDL20_DWLG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                2956
swis2-VHDL20_DWLG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2838
swis2-VHDL20_DWLG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2747
swis2-VHDL20_DWLG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2783
swis2-VHDL20_DWLG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                2724
swis2-VHDL20_DWLG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                2725
swis2-VHDL20_DWLG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2513
swis2-VHDL20_DWLH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2881
swis2-VHDL20_DWLH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2826
swis2-VHDL20_DWLH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2843
swis2-VHDL20_DWLH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3073
swis2-VHDL20_DWLH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2819
swis2-VHDL20_DWLH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2986
swis2-VHDL20_DWLH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                3014
swis2-VHDL20_DWLH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3108
swis2-VHDL20_DWLH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                3048
swis2-VHDL20_DWLH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2672
swis2-VHDL20_DWLI_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2795
swis2-VHDL20_DWLI_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2723
swis2-VHDL20_DWLI_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2769
swis2-VHDL20_DWLI_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                2904
swis2-VHDL20_DWLI_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2624
swis2-VHDL20_DWLI_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                2669
swis2-VHDL20_DWLI_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                2714
swis2-VHDL20_DWLI_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                2786
swis2-VHDL20_DWLI_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                2749
swis2-VHDL20_DWLI_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2459
swis2-VHDL20_DWMG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                3517
swis2-VHDL20_DWMG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                3373
swis2-VHDL20_DWMG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3823
swis2-VHDL20_DWMG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3810
swis2-VHDL20_DWMG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                3976
swis2-VHDL20_DWMG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                3970
swis2-VHDL20_DWMG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                3956
swis2-VHDL20_DWMG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                4024
swis2-VHDL20_DWMG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                4095
swis2-VHDL20_DWMG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                3792
swis2-VHDL20_DWMO_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2899
swis2-VHDL20_DWMO_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2718
swis2-VHDL20_DWMO_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3462
swis2-VHDL20_DWMO_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3381
swis2-VHDL20_DWMO_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                3033
swis2-VHDL20_DWMO_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                3180
swis2-VHDL20_DWMO_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                3120
swis2-VHDL20_DWMO_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3277
swis2-VHDL20_DWMO_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                3357
swis2-VHDL20_DWMO_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2986
swis2-VHDL20_DWMP_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                3312
swis2-VHDL20_DWMP_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                3207
swis2-VHDL20_DWMP_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                3207
swis2-VHDL20_DWMP_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:45                3625
swis2-VHDL20_DWMP_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                3595
swis2-VHDL20_DWMP_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                3694
swis2-VHDL20_DWMP_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                3733
swis2-VHDL20_DWMP_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3753
swis2-VHDL20_DWMP_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:45                3816
swis2-VHDL20_DWMP_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                3573
swis2-VHDL20_DWPG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2804
swis2-VHDL20_DWPG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2716
swis2-VHDL20_DWPG_190530-2010190530-dsw--0-ia5     19-Oct-2020 05:30                2716
swis2-VHDL20_DWPG_190630-2010190630-dsw--0-ia5     19-Oct-2020 06:30                2716
swis2-VHDL20_DWPG_190730-2010190730-dsw--0-ia5     19-Oct-2020 07:30                2716
swis2-VHDL20_DWPG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2733
swis2-VHDL20_DWPG_190930-2010190930-dsw--0-ia5     19-Oct-2020 09:30                2732
swis2-VHDL20_DWPG_191030-2010191030-dsw--0-ia5     19-Oct-2020 10:30                2732
swis2-VHDL20_DWPG_191130-2010191130-dsw--0-ia5     19-Oct-2020 11:30                2766
swis2-VHDL20_DWPG_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2892
swis2-VHDL20_DWPG_191330-2010191330-dsw--0-ia5     19-Oct-2020 13:30                2898
swis2-VHDL20_DWPG_191430-2010191430-dsw--0-ia5     19-Oct-2020 14:30                2948
swis2-VHDL20_DWPG_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                2970
swis2-VHDL20_DWPG_191630-2010191630-dsw--0-ia5     19-Oct-2020 16:30                3001
swis2-VHDL20_DWPG_191730-2010191730-dsw--0-ia5     19-Oct-2020 17:30                3001
swis2-VHDL20_DWPG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2830
swis2-VHDL20_DWPG_191930-2010191930-dsw--0-ia5     19-Oct-2020 19:30                2829
swis2-VHDL20_DWPG_192030-2010192030-dsw--0-ia5     19-Oct-2020 20:30                2829
swis2-VHDL20_DWPG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2735
swis2-VHDL20_DWPG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2750
swis2-VHDL20_DWPG_200530-2010200530-dsw--0-ia5     20-Oct-2020 05:30                2748
swis2-VHDL20_DWPG_200630-2010200630-dsw--0-ia5     20-Oct-2020 06:30                2748
swis2-VHDL20_DWPG_200730-2010200730-dsw--0-ia5     20-Oct-2020 07:30                2766
swis2-VHDL20_DWPG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2848
swis2-VHDL20_DWPG_200930-2010200930-dsw--0-ia5     20-Oct-2020 09:30                2847
swis2-VHDL20_DWPG_201030-2010201030-dsw--0-ia5     20-Oct-2020 10:30                2847
swis2-VHDL20_DWPG_201130-2010201130-dsw--0-ia5     20-Oct-2020 11:30                2833
swis2-VHDL20_DWPG_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2883
swis2-VHDL20_DWPG_201330-2010201330-dsw--0-ia5     20-Oct-2020 13:30                2883
swis2-VHDL20_DWPG_201430-2010201430-dsw--0-ia5     20-Oct-2020 14:30                2883
swis2-VHDL20_DWPG_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                2661
swis2-VHDL20_DWPG_201630-2010201630-dsw--0-ia5     20-Oct-2020 16:30                2661
swis2-VHDL20_DWPG_201730-2010201730-dsw--0-ia5     20-Oct-2020 17:30                2661
swis2-VHDL20_DWPG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2499
swis2-VHDL20_DWPG_201930-2010201930-dsw--0-ia5     20-Oct-2020 19:30                2498
swis2-VHDL20_DWPG_202030-2010202030-dsw--0-ia5     20-Oct-2020 20:30                2498
swis2-VHDL20_DWPH_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:30                2835
swis2-VHDL20_DWPH_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:30                2864
swis2-VHDL20_DWPH_190530-2010190530-dsw--0-ia5     19-Oct-2020 05:30                2864
swis2-VHDL20_DWPH_190630-2010190630-dsw--0-ia5     19-Oct-2020 06:30                2864
swis2-VHDL20_DWPH_190730-2010190730-dsw--0-ia5     19-Oct-2020 07:30                2864
swis2-VHDL20_DWPH_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:30                2895
swis2-VHDL20_DWPH_190930-2010190930-dsw--0-ia5     19-Oct-2020 09:30                2895
swis2-VHDL20_DWPH_191030-2010191030-dsw--0-ia5     19-Oct-2020 10:30                2895
swis2-VHDL20_DWPH_191130-2010191130-dsw--0-ia5     19-Oct-2020 11:30                2919
swis2-VHDL20_DWPH_191300-2010191300-dsw--0-ia5     19-Oct-2020 12:30                2945
swis2-VHDL20_DWPH_191330-2010191330-dsw--0-ia5     19-Oct-2020 13:30                2883
swis2-VHDL20_DWPH_191430-2010191430-dsw--0-ia5     19-Oct-2020 14:30                2872
swis2-VHDL20_DWPH_191500-2010191500-dsw--0-ia5     19-Oct-2020 15:30                3056
swis2-VHDL20_DWPH_191630-2010191630-dsw--0-ia5     19-Oct-2020 16:30                3054
swis2-VHDL20_DWPH_191730-2010191730-dsw--0-ia5     19-Oct-2020 17:30                3054
swis2-VHDL20_DWPH_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:30                2857
swis2-VHDL20_DWPH_191930-2010191930-dsw--0-ia5     19-Oct-2020 19:30                2857
swis2-VHDL20_DWPH_192030-2010192030-dsw--0-ia5     19-Oct-2020 20:30                2857
swis2-VHDL20_DWPH_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:30                2668
swis2-VHDL20_DWPH_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:30                2703
swis2-VHDL20_DWPH_200530-2010200530-dsw--0-ia5     20-Oct-2020 05:30                2701
swis2-VHDL20_DWPH_200630-2010200630-dsw--0-ia5     20-Oct-2020 06:30                2716
swis2-VHDL20_DWPH_200730-2010200730-dsw--0-ia5     20-Oct-2020 07:30                2716
swis2-VHDL20_DWPH_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:30                2662
swis2-VHDL20_DWPH_200930-2010200930-dsw--0-ia5     20-Oct-2020 09:30                2662
swis2-VHDL20_DWPH_201030-2010201030-dsw--0-ia5     20-Oct-2020 10:30                2662
swis2-VHDL20_DWPH_201130-2010201130-dsw--0-ia5     20-Oct-2020 11:30                2665
swis2-VHDL20_DWPH_201300-2010201300-dsw--0-ia5     20-Oct-2020 12:30                2675
swis2-VHDL20_DWPH_201330-2010201330-dsw--0-ia5     20-Oct-2020 13:30                2675
swis2-VHDL20_DWPH_201430-2010201430-dsw--0-ia5     20-Oct-2020 14:30                2675
swis2-VHDL20_DWPH_201500-2010201500-dsw--0-ia5     20-Oct-2020 15:30                2594
swis2-VHDL20_DWPH_201630-2010201630-dsw--0-ia5     20-Oct-2020 16:30                2594
swis2-VHDL20_DWPH_201730-2010201730-dsw--0-ia5     20-Oct-2020 17:30                2594
swis2-VHDL20_DWPH_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:30                2756
swis2-VHDL20_DWPH_201930-2010201930-dsw--0-ia5     20-Oct-2020 19:30                2756
swis2-VHDL20_DWPH_202030-2010202030-dsw--0-ia5     20-Oct-2020 20:30                2756
swis2-VHDL20_DWSG_190200-2010190200-dsw--0-ia5     19-Oct-2020 02:45                2740
swis2-VHDL20_DWSG_190400-2010190400-dsw--0-ia5     19-Oct-2020 04:45                2687
swis2-VHDL20_DWSG_190800-2010190800-dsw--0-ia5     19-Oct-2020 08:45                2715
swis2-VHDL20_DWSG_191300-2010191300-dsw--0-ia5     19-Oct-2020 13:45                3264
swis2-VHDL20_DWSG_191800-2010191800-dsw--0-ia5     19-Oct-2020 18:45                2982
swis2-VHDL20_DWSG_200200-2010200200-dsw--0-ia5     20-Oct-2020 02:45                3073
swis2-VHDL20_DWSG_200400-2010200400-dsw--0-ia5     20-Oct-2020 04:45                3224
swis2-VHDL20_DWSG_200800-2010200800-dsw--0-ia5     20-Oct-2020 08:45                3111
swis2-VHDL20_DWSG_201300-2010201300-dsw--0-ia5     20-Oct-2020 13:45                3082
swis2-VHDL20_DWSG_201800-2010201800-dsw--0-ia5     20-Oct-2020 18:45                2764
wst04-VHDL20_DWEG_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              247510
wst04-VHDL20_DWEG_190400-2010190400-omedes--0.pdf  19-Oct-2020 05:15              247054
wst04-VHDL20_DWEG_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              246907
wst04-VHDL20_DWEG_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              247583
wst04-VHDL20_DWEG_191500-2010191500-omedes--0.pdf  19-Oct-2020 15:45              247519
wst04-VHDL20_DWEG_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              247384
wst04-VHDL20_DWEG_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              247243
wst04-VHDL20_DWEG_200400-2010200400-omedes--0.pdf  20-Oct-2020 05:15              247179
wst04-VHDL20_DWEG_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              251751
wst04-VHDL20_DWEG_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              251090
wst04-VHDL20_DWEG_201500-2010201500-omedes--0.pdf  20-Oct-2020 15:45              251021
wst04-VHDL20_DWEG_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              250816
wst04-VHDL20_DWEH_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              243461
wst04-VHDL20_DWEH_190400-2010190400-omedes--0.pdf  19-Oct-2020 05:15              243550
wst04-VHDL20_DWEH_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              247312
wst04-VHDL20_DWEH_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              248214
wst04-VHDL20_DWEH_191500-2010191500-omedes--0.pdf  19-Oct-2020 15:45              248299
wst04-VHDL20_DWEH_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              247982
wst04-VHDL20_DWEH_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              247873
wst04-VHDL20_DWEH_200400-2010200400-omedes--0.pdf  20-Oct-2020 05:15              248630
wst04-VHDL20_DWEH_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              246704
wst04-VHDL20_DWEH_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              245914
wst04-VHDL20_DWEH_201500-2010201500-omedes--0.pdf  20-Oct-2020 15:45              245539
wst04-VHDL20_DWEH_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              245961
wst04-VHDL20_DWEI_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              339613
wst04-VHDL20_DWEI_190400-2010190400-omedes--0.pdf  19-Oct-2020 05:15              339683
wst04-VHDL20_DWEI_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              345876
wst04-VHDL20_DWEI_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              346213
wst04-VHDL20_DWEI_191500-2010191500-omedes--0.pdf  19-Oct-2020 15:45              346121
wst04-VHDL20_DWEI_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              346046
wst04-VHDL20_DWEI_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              345939
wst04-VHDL20_DWEI_200400-2010200400-omedes--0.pdf  20-Oct-2020 05:15              346081
wst04-VHDL20_DWEI_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              346807
wst04-VHDL20_DWEI_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              346239
wst04-VHDL20_DWEI_201500-2010201500-omedes--0.pdf  20-Oct-2020 15:45              346153
wst04-VHDL20_DWEI_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              346015
wst04-VHDL20_DWHG_190200-2010190200-oflxs888--0..> 19-Oct-2020 02:45              327009
wst04-VHDL20_DWHG_190400-2010190400-oflxs888--0..> 19-Oct-2020 04:45              327049
wst04-VHDL20_DWHG_190800-2010190800-oflxs888--0..> 19-Oct-2020 08:45              344846
wst04-VHDL20_DWHG_191300-2010191300-oflxs888--0..> 19-Oct-2020 13:45              344298
wst04-VHDL20_DWHG_191800-2010191800-oflxs888--0..> 19-Oct-2020 18:45              343519
wst04-VHDL20_DWHG_200200-2010200200-oflxs888--0..> 20-Oct-2020 02:45              344728
wst04-VHDL20_DWHG_200400-2010200400-oflxs888--0..> 20-Oct-2020 04:45              344702
wst04-VHDL20_DWHG_200800-2010200800-oflxs888--0..> 20-Oct-2020 08:45              346247
wst04-VHDL20_DWHG_201300-2010201300-oflxs888--0..> 20-Oct-2020 13:45              345750
wst04-VHDL20_DWHG_201800-2010201800-oflxs888--0..> 20-Oct-2020 18:45              345620
wst04-VHDL20_DWHH_190200-2010190200-oflxs888--0..> 19-Oct-2020 02:45              316322
wst04-VHDL20_DWHH_190400-2010190400-oflxs888--0..> 19-Oct-2020 04:45              316347
wst04-VHDL20_DWHH_190800-2010190800-oflxs888--0..> 19-Oct-2020 08:45              330363
wst04-VHDL20_DWHH_191300-2010191300-oflxs888--0..> 19-Oct-2020 13:45              330326
wst04-VHDL20_DWHH_191800-2010191800-oflxs888--0..> 19-Oct-2020 18:45              330087
wst04-VHDL20_DWHH_200200-2010200200-oflxs888--0..> 20-Oct-2020 02:45              330224
wst04-VHDL20_DWHH_200400-2010200400-oflxs888--0..> 20-Oct-2020 04:45              331228
wst04-VHDL20_DWHH_200800-2010200800-oflxs888--0..> 20-Oct-2020 08:45              334110
wst04-VHDL20_DWHH_201300-2010201300-oflxs888--0..> 20-Oct-2020 13:45              334136
wst04-VHDL20_DWHH_201800-2010201800-oflxs888--0..> 20-Oct-2020 18:45              333526
wst04-VHDL20_DWLG_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:40              239593
wst04-VHDL20_DWLG_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:40              239194
wst04-VHDL20_DWLG_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:40              242380
wst04-VHDL20_DWLG_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:40              243204
wst04-VHDL20_DWLG_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:40              243086
wst04-VHDL20_DWLG_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:40              243110
wst04-VHDL20_DWLG_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:40              242840
wst04-VHDL20_DWLG_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:40              243540
wst04-VHDL20_DWLG_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:40              243701
wst04-VHDL20_DWLG_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:40              243546
wst04-VHDL20_DWLH_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:40              240725
wst04-VHDL20_DWLH_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:40              240283
wst04-VHDL20_DWLH_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:40              242812
wst04-VHDL20_DWLH_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:40              243693
wst04-VHDL20_DWLH_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:40              243473
wst04-VHDL20_DWLH_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:40              243693
wst04-VHDL20_DWLH_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:40              243337
wst04-VHDL20_DWLH_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:40              247846
wst04-VHDL20_DWLH_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:40              247993
wst04-VHDL20_DWLH_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:40              247764
wst04-VHDL20_DWLI_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:40              239276
wst04-VHDL20_DWLI_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:40              238888
wst04-VHDL20_DWLI_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:40              243796
wst04-VHDL20_DWLI_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:40              244625
wst04-VHDL20_DWLI_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:40              243991
wst04-VHDL20_DWLI_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:40              244104
wst04-VHDL20_DWLI_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:40              243821
wst04-VHDL20_DWLI_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:40              245333
wst04-VHDL20_DWLI_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:40              245504
wst04-VHDL20_DWLI_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:40              245300
wst04-VHDL20_DWMG_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              531783
wst04-VHDL20_DWMG_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:45              531222
wst04-VHDL20_DWMG_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              538652
wst04-VHDL20_DWMG_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              538771
wst04-VHDL20_DWMG_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              538751
wst04-VHDL20_DWMG_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              539565
wst04-VHDL20_DWMG_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:45              539283
wst04-VHDL20_DWMG_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              538833
wst04-VHDL20_DWMG_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              538974
wst04-VHDL20_DWMG_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              538006
wst04-VHDL20_DWMO_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              427671
wst04-VHDL20_DWMO_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:45              427359
wst04-VHDL20_DWMO_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              432734
wst04-VHDL20_DWMO_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              432067
wst04-VHDL20_DWMO_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              430866
wst04-VHDL20_DWMO_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              432327
wst04-VHDL20_DWMO_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:45              432762
wst04-VHDL20_DWMO_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              442550
wst04-VHDL20_DWMO_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              442408
wst04-VHDL20_DWMO_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              440736
wst04-VHDL20_DWMP_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              547627
wst04-VHDL20_DWMP_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:45              548314
wst04-VHDL20_DWMP_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              557264
wst04-VHDL20_DWMP_191300-2010191300-omedes--0.pdf  19-Oct-2020 12:45              557811
wst04-VHDL20_DWMP_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              557759
wst04-VHDL20_DWMP_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              557219
wst04-VHDL20_DWMP_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:45              557977
wst04-VHDL20_DWMP_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              544235
wst04-VHDL20_DWMP_201300-2010201300-omedes--0.pdf  20-Oct-2020 12:45              544025
wst04-VHDL20_DWMP_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              543165
wst04-VHDL20_DWPG_190200-2010190200-oflxs892--0..> 19-Oct-2020 02:30              332888
wst04-VHDL20_DWPG_190400-2010190400-oflxs892--0..> 19-Oct-2020 04:30              332387
wst04-VHDL20_DWPG_190530-2010190530-oflxs892--0..> 19-Oct-2020 05:30              332355
wst04-VHDL20_DWPG_190630-2010190630-oflxs892--0..> 19-Oct-2020 06:30              332355
wst04-VHDL20_DWPG_190730-2010190730-oflxs892--0..> 19-Oct-2020 07:30              332355
wst04-VHDL20_DWPG_190800-2010190800-oflxs892--0..> 19-Oct-2020 08:30              374349
wst04-VHDL20_DWPG_190930-2010190930-oflxs892--0..> 19-Oct-2020 09:30              329760
wst04-VHDL20_DWPG_191030-2010191030-oflxs892--0..> 19-Oct-2020 10:30              329760
wst04-VHDL20_DWPG_191130-2010191130-oflxs892--0..> 19-Oct-2020 11:30              329819
wst04-VHDL20_DWPG_191300-2010191300-oflxs892--0..> 19-Oct-2020 12:30              329924
wst04-VHDL20_DWPG_191330-2010191330-oflxs892--0..> 19-Oct-2020 13:30              329966
wst04-VHDL20_DWPG_191430-2010191430-oflxs892--0..> 19-Oct-2020 14:30              330141
wst04-VHDL20_DWPG_191500-2010191500-oflxs892--0..> 19-Oct-2020 15:30              330068
wst04-VHDL20_DWPG_191630-2010191630-oflxs892--0..> 19-Oct-2020 16:30              329949
wst04-VHDL20_DWPG_191730-2010191730-oflxs892--0..> 19-Oct-2020 17:30              330046
wst04-VHDL20_DWPG_191800-2010191800-oflxs892--0..> 19-Oct-2020 18:30              329047
wst04-VHDL20_DWPG_191930-2010191930-oflxs892--0..> 19-Oct-2020 19:30              329334
wst04-VHDL20_DWPG_192030-2010192030-oflxs892--0..> 19-Oct-2020 20:30              329334
wst04-VHDL20_DWPG_200200-2010200200-oflxs892--0..> 20-Oct-2020 02:30              329692
wst04-VHDL20_DWPG_200400-2010200400-oflxs892--0..> 20-Oct-2020 04:30              329501
wst04-VHDL20_DWPG_200530-2010200530-oflxs892--0..> 20-Oct-2020 05:30              329323
wst04-VHDL20_DWPG_200630-2010200630-oflxs892--0..> 20-Oct-2020 06:30              329323
wst04-VHDL20_DWPG_200730-2010200730-oflxs892--0..> 20-Oct-2020 07:30              329339
wst04-VHDL20_DWPG_200800-2010200800-oflxs892--0..> 20-Oct-2020 08:30              373183
wst04-VHDL20_DWPG_200930-2010200930-oflxs892--0..> 20-Oct-2020 09:30              349802
wst04-VHDL20_DWPG_201030-2010201030-oflxs892--0..> 20-Oct-2020 10:30              349802
wst04-VHDL20_DWPG_201130-2010201130-oflxs892--0..> 20-Oct-2020 11:30              350195
wst04-VHDL20_DWPG_201300-2010201300-oflxs892--0..> 20-Oct-2020 12:30              350279
wst04-VHDL20_DWPG_201330-2010201330-oflxs892--0..> 20-Oct-2020 13:30              350239
wst04-VHDL20_DWPG_201430-2010201430-oflxs892--0..> 20-Oct-2020 14:30              350677
wst04-VHDL20_DWPG_201500-2010201500-oflxs892--0..> 20-Oct-2020 15:30              350110
wst04-VHDL20_DWPG_201630-2010201630-oflxs892--0..> 20-Oct-2020 16:30              350097
wst04-VHDL20_DWPG_201730-2010201730-oflxs892--0..> 20-Oct-2020 17:30              350097
wst04-VHDL20_DWPG_201800-2010201800-oflxs892--0..> 20-Oct-2020 18:30              349978
wst04-VHDL20_DWPG_201930-2010201930-oflxs892--0..> 20-Oct-2020 19:30              349943
wst04-VHDL20_DWPG_202030-2010202030-oflxs892--0..> 20-Oct-2020 20:30              349943
wst04-VHDL20_DWPH_190200-2010190200-oflxs892--0..> 19-Oct-2020 02:30              247724
wst04-VHDL20_DWPH_190400-2010190400-oflxs892--0..> 19-Oct-2020 04:30              247102
wst04-VHDL20_DWPH_190530-2010190530-oflxs892--0..> 19-Oct-2020 05:30              247051
wst04-VHDL20_DWPH_190630-2010190630-oflxs892--0..> 19-Oct-2020 06:30              247051
wst04-VHDL20_DWPH_190730-2010190730-oflxs892--0..> 19-Oct-2020 07:30              247051
wst04-VHDL20_DWPH_190800-2010190800-oflxs892--0..> 19-Oct-2020 08:30              291252
wst04-VHDL20_DWPH_190930-2010190930-oflxs892--0..> 19-Oct-2020 09:30              246634
wst04-VHDL20_DWPH_191030-2010191030-oflxs892--0..> 19-Oct-2020 10:30              246633
wst04-VHDL20_DWPH_191130-2010191130-oflxs892--0..> 19-Oct-2020 11:30              246605
wst04-VHDL20_DWPH_191300-2010191300-oflxs892--0..> 19-Oct-2020 12:30              246062
wst04-VHDL20_DWPH_191330-2010191330-oflxs892--0..> 19-Oct-2020 13:30              246005
wst04-VHDL20_DWPH_191430-2010191430-oflxs892--0..> 19-Oct-2020 14:30              246040
wst04-VHDL20_DWPH_191500-2010191500-oflxs892--0..> 19-Oct-2020 15:30              246746
wst04-VHDL20_DWPH_191630-2010191630-oflxs892--0..> 19-Oct-2020 16:30              246730
wst04-VHDL20_DWPH_191730-2010191730-oflxs892--0..> 19-Oct-2020 17:30              246727
wst04-VHDL20_DWPH_191800-2010191800-oflxs892--0..> 19-Oct-2020 18:30              291199
wst04-VHDL20_DWPH_191930-2010191930-oflxs892--0..> 19-Oct-2020 19:30              246594
wst04-VHDL20_DWPH_192030-2010192030-oflxs892--0..> 19-Oct-2020 20:30              246594
wst04-VHDL20_DWPH_200200-2010200200-oflxs892--0..> 20-Oct-2020 02:30              246187
wst04-VHDL20_DWPH_200400-2010200400-oflxs892--0..> 20-Oct-2020 04:30              245992
wst04-VHDL20_DWPH_200530-2010200530-oflxs892--0..> 20-Oct-2020 05:30              245916
wst04-VHDL20_DWPH_200630-2010200630-oflxs892--0..> 20-Oct-2020 06:30              245830
wst04-VHDL20_DWPH_200730-2010200730-oflxs892--0..> 20-Oct-2020 07:30              245830
wst04-VHDL20_DWPH_200800-2010200800-oflxs892--0..> 20-Oct-2020 08:30              290391
wst04-VHDL20_DWPH_200930-2010200930-oflxs892--0..> 20-Oct-2020 09:30              252517
wst04-VHDL20_DWPH_201030-2010201030-oflxs892--0..> 20-Oct-2020 10:30              252517
wst04-VHDL20_DWPH_201130-2010201130-oflxs892--0..> 20-Oct-2020 11:30              252537
wst04-VHDL20_DWPH_201300-2010201300-oflxs892--0..> 20-Oct-2020 12:30              252560
wst04-VHDL20_DWPH_201330-2010201330-oflxs892--0..> 20-Oct-2020 13:30              252549
wst04-VHDL20_DWPH_201430-2010201430-oflxs892--0..> 20-Oct-2020 14:30              252549
wst04-VHDL20_DWPH_201500-2010201500-oflxs892--0..> 20-Oct-2020 15:30              252959
wst04-VHDL20_DWPH_201630-2010201630-oflxs892--0..> 20-Oct-2020 16:30              252934
wst04-VHDL20_DWPH_201730-2010201730-oflxs892--0..> 20-Oct-2020 17:30              252934
wst04-VHDL20_DWPH_201800-2010201800-oflxs892--0..> 20-Oct-2020 18:30              297602
wst04-VHDL20_DWPH_201930-2010201930-oflxs892--0..> 20-Oct-2020 19:30              252990
wst04-VHDL20_DWPH_202030-2010202030-oflxs892--0..> 20-Oct-2020 20:30              252990
wst04-VHDL20_DWSG_190200-2010190200-omedes--0.pdf  19-Oct-2020 02:45              339433
wst04-VHDL20_DWSG_190400-2010190400-omedes--0.pdf  19-Oct-2020 04:45              339413
wst04-VHDL20_DWSG_190800-2010190800-omedes--0.pdf  19-Oct-2020 08:45              340078
wst04-VHDL20_DWSG_191300-2010191300-omedes--0.pdf  19-Oct-2020 13:45              340666
wst04-VHDL20_DWSG_191800-2010191800-omedes--0.pdf  19-Oct-2020 18:45              340044
wst04-VHDL20_DWSG_200200-2010200200-omedes--0.pdf  20-Oct-2020 02:45              340254
wst04-VHDL20_DWSG_200400-2010200400-omedes--0.pdf  20-Oct-2020 04:45              340804
wst04-VHDL20_DWSG_200800-2010200800-omedes--0.pdf  20-Oct-2020 08:45              336408
wst04-VHDL20_DWSG_201300-2010201300-omedes--0.pdf  20-Oct-2020 13:45              336717
wst04-VHDL20_DWSG_201800-2010201800-omedes--0.pdf  20-Oct-2020 18:45              336484