Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_020600                                 02-Jun-2020 09:29                2312
FPDL13_DWMZ_030600                                 03-Jun-2020 07:07                2465
SXDL31_DWAV_011800                                 01-Jun-2020 17:54                7221
SXDL31_DWAV_020800                                 02-Jun-2020 07:04               14127
SXDL31_DWAV_021800                                 02-Jun-2020 16:49               14802
SXDL31_DWAV_030800                                 03-Jun-2020 07:45               11378
SXDL31_DWAV_031800                                 03-Jun-2020 16:25               10903
SXDL33_DWAV_020000                                 02-Jun-2020 10:35                6938
SXDL33_DWAV_030000                                 03-Jun-2020 09:33               14445
ber01-FWDL39_DWMS_021230-2006021230-dsw--0-ia5     02-Jun-2020 12:37                1107
ber01-FWDL39_DWMS_031230-2006031230-dsw--0-ia5     03-Jun-2020 11:32                1332
ber01-VHDL13_DWEH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:28                2099
ber01-VHDL13_DWEH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:28                2595
ber01-VHDL13_DWEH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:58                2472
ber01-VHDL13_DWEH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:28                3056
ber01-VHDL13_DWEH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:28                3234
ber01-VHDL13_DWEH_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:28                3437
ber01-VHDL13_DWEH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:28                3436
ber01-VHDL13_DWEH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:28                3590
ber01-VHDL13_DWEH_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:16                3483
ber01-VHDL13_DWEH_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 05:15                3487
ber01-VHDL13_DWEH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:28                3507
ber01-VHDL13_DWEH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:28                3611
ber01-VHDL13_DWEH_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:28                3794
ber01-VHDL13_DWHG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1923
ber01-VHDL13_DWHG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2069
ber01-VHDL13_DWHG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2081
ber01-VHDL13_DWHG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2309
ber01-VHDL13_DWHG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                2668
ber01-VHDL13_DWHG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2462
ber01-VHDL13_DWHG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2801
ber01-VHDL13_DWHG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2858
ber01-VHDL13_DWHG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2975
ber01-VHDL13_DWHG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3072
ber01-VHDL13_DWHG_031300_COR-2006031300-dsw--0-ia5 03-Jun-2020 14:05                3102
ber01-VHDL13_DWHH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                2052
ber01-VHDL13_DWHH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2224
ber01-VHDL13_DWHH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2239
ber01-VHDL13_DWHH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2381
ber01-VHDL13_DWHH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                2503
ber01-VHDL13_DWHH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2338
ber01-VHDL13_DWHH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2762
ber01-VHDL13_DWHH_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2797
ber01-VHDL13_DWHH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3159
ber01-VHDL13_DWHH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3266
ber01-VHDL13_DWHH_031300_COR-2006031300-dsw--0-ia5 03-Jun-2020 15:21                3308
ber01-VHDL13_DWLG_011733-2006011733-dsw--0-ia5     01-Jun-2020 17:33                1945
ber01-VHDL13_DWLG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1794
ber01-VHDL13_DWLG_011933-2006011933-dsw--0-ia5     01-Jun-2020 19:33                1822
ber01-VHDL13_DWLG_012033-2006012033-dsw--0-ia5     01-Jun-2020 20:33                1822
ber01-VHDL13_DWLG_020033-2006020033-dsw--0-ia5     02-Jun-2020 00:33                2427
ber01-VHDL13_DWLG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2454
ber01-VHDL13_DWLG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2489
ber01-VHDL13_DWLG_020533-2006020533-dsw--0-ia5     02-Jun-2020 05:33                2517
ber01-VHDL13_DWLG_020633-2006020633-dsw--0-ia5     02-Jun-2020 06:33                2517
ber01-VHDL13_DWLG_020733-2006020733-dsw--0-ia5     02-Jun-2020 07:33                2517
ber01-VHDL13_DWLG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2469
ber01-VHDL13_DWLG_020933-2006020933-dsw--0-ia5     02-Jun-2020 09:33                2500
ber01-VHDL13_DWLG_021033-2006021033-dsw--0-ia5     02-Jun-2020 10:33                2500
ber01-VHDL13_DWLG_021133-2006021133-dsw--0-ia5     02-Jun-2020 11:33                2504
ber01-VHDL13_DWLG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                2444
ber01-VHDL13_DWLG_021333-2006021333-dsw--0-ia5     02-Jun-2020 13:33                2810
ber01-VHDL13_DWLG_021433-2006021433-dsw--0-ia5     02-Jun-2020 14:33                2810
ber01-VHDL13_DWLG_021533-2006021533-dsw--0-ia5     02-Jun-2020 15:33                2783
ber01-VHDL13_DWLG_021633-2006021633-dsw--0-ia5     02-Jun-2020 16:33                2783
ber01-VHDL13_DWLG_021733-2006021733-dsw--0-ia5     02-Jun-2020 17:33                2676
ber01-VHDL13_DWLG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2332
ber01-VHDL13_DWLG_021933-2006021933-dsw--0-ia5     02-Jun-2020 19:33                2360
ber01-VHDL13_DWLG_022033-2006022033-dsw--0-ia5     02-Jun-2020 20:33                2415
ber01-VHDL13_DWLG_030033-2006030033-dsw--0-ia5     03-Jun-2020 00:33                2505
ber01-VHDL13_DWLG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2538
ber01-VHDL13_DWLG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2631
ber01-VHDL13_DWLG_030533-2006030533-dsw--0-ia5     03-Jun-2020 05:33                2659
ber01-VHDL13_DWLG_030633-2006030633-dsw--0-ia5     03-Jun-2020 06:33                2659
ber01-VHDL13_DWLG_030733-2006030733-dsw--0-ia5     03-Jun-2020 07:33                2659
ber01-VHDL13_DWLG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2625
ber01-VHDL13_DWLG_030933-2006030933-dsw--0-ia5     03-Jun-2020 09:33                2656
ber01-VHDL13_DWLG_031033-2006031033-dsw--0-ia5     03-Jun-2020 10:33                2613
ber01-VHDL13_DWLG_031133-2006031133-dsw--0-ia5     03-Jun-2020 11:33                2613
ber01-VHDL13_DWLG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                2591
ber01-VHDL13_DWLG_031333-2006031333-dsw--0-ia5     03-Jun-2020 13:33                2549
ber01-VHDL13_DWLG_031433-2006031433-dsw--0-ia5     03-Jun-2020 14:33                2549
ber01-VHDL13_DWLG_031533-2006031533-dsw--0-ia5     03-Jun-2020 15:33                2549
ber01-VHDL13_DWLG_031633-2006031633-dsw--0-ia5     03-Jun-2020 16:33                2549
ber01-VHDL13_DWLH_011733-2006011733-dsw--0-ia5     01-Jun-2020 17:33                1850
ber01-VHDL13_DWLH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1703
ber01-VHDL13_DWLH_011933-2006011933-dsw--0-ia5     01-Jun-2020 19:33                1731
ber01-VHDL13_DWLH_012033-2006012033-dsw--0-ia5     01-Jun-2020 20:33                1731
ber01-VHDL13_DWLH_020033-2006020033-dsw--0-ia5     02-Jun-2020 00:33                1998
ber01-VHDL13_DWLH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                1970
ber01-VHDL13_DWLH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                1936
ber01-VHDL13_DWLH_020533-2006020533-dsw--0-ia5     02-Jun-2020 05:33                1964
ber01-VHDL13_DWLH_020633-2006020633-dsw--0-ia5     02-Jun-2020 06:33                1964
ber01-VHDL13_DWLH_020733-2006020733-dsw--0-ia5     02-Jun-2020 07:33                1964
ber01-VHDL13_DWLH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                1936
ber01-VHDL13_DWLH_020933-2006020933-dsw--0-ia5     02-Jun-2020 09:33                1964
ber01-VHDL13_DWLH_021033-2006021033-dsw--0-ia5     02-Jun-2020 10:33                1964
ber01-VHDL13_DWLH_021133-2006021133-dsw--0-ia5     02-Jun-2020 11:33                1929
ber01-VHDL13_DWLH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                1883
ber01-VHDL13_DWLH_021333-2006021333-dsw--0-ia5     02-Jun-2020 13:33                2187
ber01-VHDL13_DWLH_021433-2006021433-dsw--0-ia5     02-Jun-2020 14:33                2187
ber01-VHDL13_DWLH_021533-2006021533-dsw--0-ia5     02-Jun-2020 15:33                2187
ber01-VHDL13_DWLH_021633-2006021633-dsw--0-ia5     02-Jun-2020 16:33                2187
ber01-VHDL13_DWLH_021733-2006021733-dsw--0-ia5     02-Jun-2020 17:33                2245
ber01-VHDL13_DWLH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2112
ber01-VHDL13_DWLH_021933-2006021933-dsw--0-ia5     02-Jun-2020 19:33                2140
ber01-VHDL13_DWLH_022033-2006022033-dsw--0-ia5     02-Jun-2020 20:33                2195
ber01-VHDL13_DWLH_030033-2006030033-dsw--0-ia5     03-Jun-2020 00:33                2348
ber01-VHDL13_DWLH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2451
ber01-VHDL13_DWLH_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2512
ber01-VHDL13_DWLH_030533-2006030533-dsw--0-ia5     03-Jun-2020 05:33                2540
ber01-VHDL13_DWLH_030633-2006030633-dsw--0-ia5     03-Jun-2020 06:33                2540
ber01-VHDL13_DWLH_030733-2006030733-dsw--0-ia5     03-Jun-2020 07:33                2540
ber01-VHDL13_DWLH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2538
ber01-VHDL13_DWLH_030933-2006030933-dsw--0-ia5     03-Jun-2020 09:33                2566
ber01-VHDL13_DWLH_031033-2006031033-dsw--0-ia5     03-Jun-2020 10:33                2536
ber01-VHDL13_DWLH_031133-2006031133-dsw--0-ia5     03-Jun-2020 11:33                2536
ber01-VHDL13_DWLH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                2514
ber01-VHDL13_DWLH_031333-2006031333-dsw--0-ia5     03-Jun-2020 13:33                2495
ber01-VHDL13_DWLH_031433-2006031433-dsw--0-ia5     03-Jun-2020 14:33                2495
ber01-VHDL13_DWLH_031533-2006031533-dsw--0-ia5     03-Jun-2020 15:33                2495
ber01-VHDL13_DWLH_031633-2006031633-dsw--0-ia5     03-Jun-2020 16:33                2495
ber01-VHDL13_DWLI_011733-2006011733-dsw--0-ia5     01-Jun-2020 17:33                1851
ber01-VHDL13_DWLI_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1700
ber01-VHDL13_DWLI_011933-2006011933-dsw--0-ia5     01-Jun-2020 19:33                1728
ber01-VHDL13_DWLI_012033-2006012033-dsw--0-ia5     01-Jun-2020 20:33                1728
ber01-VHDL13_DWLI_020033-2006020033-dsw--0-ia5     02-Jun-2020 00:33                2002
ber01-VHDL13_DWLI_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                1974
ber01-VHDL13_DWLI_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                1948
ber01-VHDL13_DWLI_020533-2006020533-dsw--0-ia5     02-Jun-2020 05:33                1976
ber01-VHDL13_DWLI_020633-2006020633-dsw--0-ia5     02-Jun-2020 06:33                1976
ber01-VHDL13_DWLI_020733-2006020733-dsw--0-ia5     02-Jun-2020 07:33                1976
ber01-VHDL13_DWLI_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                1948
ber01-VHDL13_DWLI_020933-2006020933-dsw--0-ia5     02-Jun-2020 09:33                1976
ber01-VHDL13_DWLI_021033-2006021033-dsw--0-ia5     02-Jun-2020 10:33                1976
ber01-VHDL13_DWLI_021133-2006021133-dsw--0-ia5     02-Jun-2020 11:33                1950
ber01-VHDL13_DWLI_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                1904
ber01-VHDL13_DWLI_021333-2006021333-dsw--0-ia5     02-Jun-2020 13:33                2208
ber01-VHDL13_DWLI_021433-2006021433-dsw--0-ia5     02-Jun-2020 14:33                2208
ber01-VHDL13_DWLI_021533-2006021533-dsw--0-ia5     02-Jun-2020 15:33                2208
ber01-VHDL13_DWLI_021633-2006021633-dsw--0-ia5     02-Jun-2020 16:33                2208
ber01-VHDL13_DWLI_021733-2006021733-dsw--0-ia5     02-Jun-2020 17:33                2256
ber01-VHDL13_DWLI_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2119
ber01-VHDL13_DWLI_021933-2006021933-dsw--0-ia5     02-Jun-2020 19:33                2147
ber01-VHDL13_DWLI_022033-2006022033-dsw--0-ia5     02-Jun-2020 20:33                2202
ber01-VHDL13_DWLI_030033-2006030033-dsw--0-ia5     03-Jun-2020 00:33                2360
ber01-VHDL13_DWLI_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2453
ber01-VHDL13_DWLI_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2514
ber01-VHDL13_DWLI_030533-2006030533-dsw--0-ia5     03-Jun-2020 05:33                2542
ber01-VHDL13_DWLI_030633-2006030633-dsw--0-ia5     03-Jun-2020 06:33                2542
ber01-VHDL13_DWLI_030733-2006030733-dsw--0-ia5     03-Jun-2020 07:33                2570
ber01-VHDL13_DWLI_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2540
ber01-VHDL13_DWLI_030933-2006030933-dsw--0-ia5     03-Jun-2020 09:33                2568
ber01-VHDL13_DWLI_031033-2006031033-dsw--0-ia5     03-Jun-2020 10:33                2538
ber01-VHDL13_DWLI_031133-2006031133-dsw--0-ia5     03-Jun-2020 11:33                2538
ber01-VHDL13_DWLI_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                2516
ber01-VHDL13_DWLI_031333-2006031333-dsw--0-ia5     03-Jun-2020 13:33                2493
ber01-VHDL13_DWLI_031433-2006031433-dsw--0-ia5     03-Jun-2020 14:33                2493
ber01-VHDL13_DWLI_031533-2006031533-dsw--0-ia5     03-Jun-2020 15:33                2493
ber01-VHDL13_DWLI_031633-2006031633-dsw--0-ia5     03-Jun-2020 16:33                2493
ber01-VHDL13_DWMG_011700-2006011700-dsw--0-ia5     01-Jun-2020 17:30                1999
ber01-VHDL13_DWMG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1762
ber01-VHDL13_DWMG_011900-2006011900-dsw--0-ia5     01-Jun-2020 19:30                1839
ber01-VHDL13_DWMG_012000-2006012000-dsw--0-ia5     01-Jun-2020 20:30                1849
ber01-VHDL13_DWMG_012100-2006012100-dsw--0-ia5     01-Jun-2020 21:30                1849
ber01-VHDL13_DWMG_012200-2006012200-dsw--0-ia5     01-Jun-2020 22:30                2042
ber01-VHDL13_DWMG_012300-2006012300-dsw--0-ia5     01-Jun-2020 23:30                2042
ber01-VHDL13_DWMG_020000-2006020000-dsw--0-ia5     02-Jun-2020 00:30                2042
ber01-VHDL13_DWMG_020100-2006020100-dsw--0-ia5     02-Jun-2020 01:30                2042
ber01-VHDL13_DWMG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2042
ber01-VHDL13_DWMG_020300-2006020300-dsw--0-ia5     02-Jun-2020 03:30                2059
ber01-VHDL13_DWMG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2064
ber01-VHDL13_DWMG_020500-2006020500-dsw--0-ia5     02-Jun-2020 05:30                2064
ber01-VHDL13_DWMG_020600-2006020600-dsw--0-ia5     02-Jun-2020 06:30                2277
ber01-VHDL13_DWMG_020700-2006020700-dsw--0-ia5     02-Jun-2020 07:30                2277
ber01-VHDL13_DWMG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2250
ber01-VHDL13_DWMG_020900-2006020900-dsw--0-ia5     02-Jun-2020 09:30                2250
ber01-VHDL13_DWMG_021000-2006021000-dsw--0-ia5     02-Jun-2020 10:30                2694
ber01-VHDL13_DWMG_021100-2006021100-dsw--0-ia5     02-Jun-2020 11:30                2694
ber01-VHDL13_DWMG_021200-2006021200-dsw--0-ia5     02-Jun-2020 12:30                2694
ber01-VHDL13_DWMG_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2694
ber01-VHDL13_DWMG_021400-2006021400-dsw--0-ia5     02-Jun-2020 14:30                2766
ber01-VHDL13_DWMG_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:30                2820
ber01-VHDL13_DWMG_021600-2006021600-dsw--0-ia5     02-Jun-2020 16:30                2820
ber01-VHDL13_DWMG_021700-2006021700-dsw--0-ia5     02-Jun-2020 17:30                2820
ber01-VHDL13_DWMG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2270
ber01-VHDL13_DWMG_021900-2006021900-dsw--0-ia5     02-Jun-2020 19:30                2241
ber01-VHDL13_DWMG_022000-2006022000-dsw--0-ia5     02-Jun-2020 20:30                2249
ber01-VHDL13_DWMG_022100-2006022100-dsw--0-ia5     02-Jun-2020 21:30                2249
ber01-VHDL13_DWMG_022200-2006022200-dsw--0-ia5     02-Jun-2020 22:30                2374
ber01-VHDL13_DWMG_022300-2006022300-dsw--0-ia5     02-Jun-2020 23:30                2374
ber01-VHDL13_DWMG_030000-2006030000-dsw--0-ia5     03-Jun-2020 00:30                2374
ber01-VHDL13_DWMG_030100-2006030100-dsw--0-ia5     03-Jun-2020 01:30                2374
ber01-VHDL13_DWMG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2374
ber01-VHDL13_DWMG_030300-2006030300-dsw--0-ia5     03-Jun-2020 03:30                2367
ber01-VHDL13_DWMG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2365
ber01-VHDL13_DWMG_030500-2006030500-dsw--0-ia5     03-Jun-2020 05:30                2365
ber01-VHDL13_DWMG_030600-2006030600-dsw--0-ia5     03-Jun-2020 06:30                2365
ber01-VHDL13_DWMG_030700-2006030700-dsw--0-ia5     03-Jun-2020 07:30                2802
ber01-VHDL13_DWMG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2814
ber01-VHDL13_DWMG_030900-2006030900-dsw--0-ia5     03-Jun-2020 09:30                2814
ber01-VHDL13_DWMG_031000-2006031000-dsw--0-ia5     03-Jun-2020 10:30                2836
ber01-VHDL13_DWMG_031100-2006031100-dsw--0-ia5     03-Jun-2020 11:30                2836
ber01-VHDL13_DWMG_031200-2006031200-dsw--0-ia5     03-Jun-2020 12:30                2769
ber01-VHDL13_DWMG_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                2706
ber01-VHDL13_DWMG_031400-2006031400-dsw--0-ia5     03-Jun-2020 14:30                2706
ber01-VHDL13_DWMG_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                2706
ber01-VHDL13_DWMG_031600-2006031600-dsw--0-ia5     03-Jun-2020 16:30                2706
ber01-VHDL13_DWMO_011700-2006011700-dsw--0-ia5     01-Jun-2020 17:30                1894
ber01-VHDL13_DWMO_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1758
ber01-VHDL13_DWMO_011900-2006011900-dsw--0-ia5     01-Jun-2020 19:30                1854
ber01-VHDL13_DWMO_012000-2006012000-dsw--0-ia5     01-Jun-2020 20:30                1880
ber01-VHDL13_DWMO_012100-2006012100-dsw--0-ia5     01-Jun-2020 21:30                1880
ber01-VHDL13_DWMO_012200-2006012200-dsw--0-ia5     01-Jun-2020 22:30                2236
ber01-VHDL13_DWMO_012300-2006012300-dsw--0-ia5     01-Jun-2020 23:30                2236
ber01-VHDL13_DWMO_020000-2006020000-dsw--0-ia5     02-Jun-2020 00:30                2236
ber01-VHDL13_DWMO_020100-2006020100-dsw--0-ia5     02-Jun-2020 01:30                2236
ber01-VHDL13_DWMO_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2236
ber01-VHDL13_DWMO_020300-2006020300-dsw--0-ia5     02-Jun-2020 03:30                2253
ber01-VHDL13_DWMO_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2261
ber01-VHDL13_DWMO_020500-2006020500-dsw--0-ia5     02-Jun-2020 05:30                2261
ber01-VHDL13_DWMO_020600-2006020600-dsw--0-ia5     02-Jun-2020 06:30                2284
ber01-VHDL13_DWMO_020700-2006020700-dsw--0-ia5     02-Jun-2020 07:30                2284
ber01-VHDL13_DWMO_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2322
ber01-VHDL13_DWMO_020900-2006020900-dsw--0-ia5     02-Jun-2020 09:30                2294
ber01-VHDL13_DWMO_021000-2006021000-dsw--0-ia5     02-Jun-2020 10:30                2672
ber01-VHDL13_DWMO_021100-2006021100-dsw--0-ia5     02-Jun-2020 11:30                2672
ber01-VHDL13_DWMO_021200-2006021200-dsw--0-ia5     02-Jun-2020 12:30                2672
ber01-VHDL13_DWMO_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2672
ber01-VHDL13_DWMO_021400-2006021400-dsw--0-ia5     02-Jun-2020 14:30                2666
ber01-VHDL13_DWMO_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:30                2566
ber01-VHDL13_DWMO_021600-2006021600-dsw--0-ia5     02-Jun-2020 16:30                2566
ber01-VHDL13_DWMO_021700-2006021700-dsw--0-ia5     02-Jun-2020 17:30                2566
ber01-VHDL13_DWMO_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2358
ber01-VHDL13_DWMO_021900-2006021900-dsw--0-ia5     02-Jun-2020 19:30                2237
ber01-VHDL13_DWMO_022000-2006022000-dsw--0-ia5     02-Jun-2020 20:30                2261
ber01-VHDL13_DWMO_022100-2006022100-dsw--0-ia5     02-Jun-2020 21:30                2261
ber01-VHDL13_DWMO_022200-2006022200-dsw--0-ia5     02-Jun-2020 22:30                2439
ber01-VHDL13_DWMO_022300-2006022300-dsw--0-ia5     02-Jun-2020 23:30                2439
ber01-VHDL13_DWMO_030000-2006030000-dsw--0-ia5     03-Jun-2020 00:30                2439
ber01-VHDL13_DWMO_030100-2006030100-dsw--0-ia5     03-Jun-2020 01:30                2439
ber01-VHDL13_DWMO_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2439
ber01-VHDL13_DWMO_030300-2006030300-dsw--0-ia5     03-Jun-2020 03:30                2439
ber01-VHDL13_DWMO_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2437
ber01-VHDL13_DWMO_030500-2006030500-dsw--0-ia5     03-Jun-2020 05:30                2437
ber01-VHDL13_DWMO_030600-2006030600-dsw--0-ia5     03-Jun-2020 06:30                2437
ber01-VHDL13_DWMO_030700-2006030700-dsw--0-ia5     03-Jun-2020 07:30                2774
ber01-VHDL13_DWMO_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2808
ber01-VHDL13_DWMO_030900-2006030900-dsw--0-ia5     03-Jun-2020 09:30                2780
ber01-VHDL13_DWMO_031000-2006031000-dsw--0-ia5     03-Jun-2020 10:30                2806
ber01-VHDL13_DWMO_031100-2006031100-dsw--0-ia5     03-Jun-2020 11:30                2806
ber01-VHDL13_DWMO_031200-2006031200-dsw--0-ia5     03-Jun-2020 12:30                2803
ber01-VHDL13_DWMO_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                2744
ber01-VHDL13_DWMO_031400-2006031400-dsw--0-ia5     03-Jun-2020 14:30                2744
ber01-VHDL13_DWMO_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                2744
ber01-VHDL13_DWMO_031600-2006031600-dsw--0-ia5     03-Jun-2020 16:30                2744
ber01-VHDL13_DWMP_011700-2006011700-dsw--0-ia5     01-Jun-2020 17:30                2229
ber01-VHDL13_DWMP_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1922
ber01-VHDL13_DWMP_011900-2006011900-dsw--0-ia5     01-Jun-2020 19:30                1947
ber01-VHDL13_DWMP_012000-2006012000-dsw--0-ia5     01-Jun-2020 20:30                1913
ber01-VHDL13_DWMP_012100-2006012100-dsw--0-ia5     01-Jun-2020 21:30                1913
ber01-VHDL13_DWMP_012200-2006012200-dsw--0-ia5     01-Jun-2020 22:30                2146
ber01-VHDL13_DWMP_012300-2006012300-dsw--0-ia5     01-Jun-2020 23:30                2146
ber01-VHDL13_DWMP_020000-2006020000-dsw--0-ia5     02-Jun-2020 00:30                2146
ber01-VHDL13_DWMP_020100-2006020100-dsw--0-ia5     02-Jun-2020 01:30                2146
ber01-VHDL13_DWMP_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2146
ber01-VHDL13_DWMP_020300-2006020300-dsw--0-ia5     02-Jun-2020 03:30                2205
ber01-VHDL13_DWMP_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2210
ber01-VHDL13_DWMP_020500-2006020500-dsw--0-ia5     02-Jun-2020 05:30                2210
ber01-VHDL13_DWMP_020600-2006020600-dsw--0-ia5     02-Jun-2020 06:30                2519
ber01-VHDL13_DWMP_020700-2006020700-dsw--0-ia5     02-Jun-2020 07:30                2519
ber01-VHDL13_DWMP_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2496
ber01-VHDL13_DWMP_020900-2006020900-dsw--0-ia5     02-Jun-2020 09:30                2496
ber01-VHDL13_DWMP_021000-2006021000-dsw--0-ia5     02-Jun-2020 10:30                2870
ber01-VHDL13_DWMP_021100-2006021100-dsw--0-ia5     02-Jun-2020 11:30                2870
ber01-VHDL13_DWMP_021200-2006021200-dsw--0-ia5     02-Jun-2020 12:30                2870
ber01-VHDL13_DWMP_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2870
ber01-VHDL13_DWMP_021400-2006021400-dsw--0-ia5     02-Jun-2020 14:30                2907
ber01-VHDL13_DWMP_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:30                2837
ber01-VHDL13_DWMP_021600-2006021600-dsw--0-ia5     02-Jun-2020 16:30                2837
ber01-VHDL13_DWMP_021700-2006021700-dsw--0-ia5     02-Jun-2020 17:30                2837
ber01-VHDL13_DWMP_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2551
ber01-VHDL13_DWMP_021900-2006021900-dsw--0-ia5     02-Jun-2020 19:30                2390
ber01-VHDL13_DWMP_022000-2006022000-dsw--0-ia5     02-Jun-2020 20:30                2419
ber01-VHDL13_DWMP_022100-2006022100-dsw--0-ia5     02-Jun-2020 21:30                2419
ber01-VHDL13_DWMP_022200-2006022200-dsw--0-ia5     02-Jun-2020 22:30                2640
ber01-VHDL13_DWMP_022300-2006022300-dsw--0-ia5     02-Jun-2020 23:30                2640
ber01-VHDL13_DWMP_030000-2006030000-dsw--0-ia5     03-Jun-2020 00:30                2640
ber01-VHDL13_DWMP_030100-2006030100-dsw--0-ia5     03-Jun-2020 01:30                2640
ber01-VHDL13_DWMP_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2640
ber01-VHDL13_DWMP_030300-2006030300-dsw--0-ia5     03-Jun-2020 03:30                2691
ber01-VHDL13_DWMP_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2691
ber01-VHDL13_DWMP_030500-2006030500-dsw--0-ia5     03-Jun-2020 05:30                2691
ber01-VHDL13_DWMP_030600-2006030600-dsw--0-ia5     03-Jun-2020 06:30                2691
ber01-VHDL13_DWMP_030700-2006030700-dsw--0-ia5     03-Jun-2020 07:30                2691
ber01-VHDL13_DWMP_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2995
ber01-VHDL13_DWMP_030900-2006030900-dsw--0-ia5     03-Jun-2020 09:30                2995
ber01-VHDL13_DWMP_031000-2006031000-dsw--0-ia5     03-Jun-2020 10:30                3014
ber01-VHDL13_DWMP_031100-2006031100-dsw--0-ia5     03-Jun-2020 11:30                3014
ber01-VHDL13_DWMP_031200-2006031200-dsw--0-ia5     03-Jun-2020 12:30                2998
ber01-VHDL13_DWMP_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                2991
ber01-VHDL13_DWMP_031400-2006031400-dsw--0-ia5     03-Jun-2020 14:30                2991
ber01-VHDL13_DWMP_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                2991
ber01-VHDL13_DWMP_031600-2006031600-dsw--0-ia5     03-Jun-2020 16:30                2991
ber01-VHDL13_DWOG_011700-2006011700-dsw--0-ia5     01-Jun-2020 17:30                2971
ber01-VHDL13_DWOG_020100-2006020100-dsw--0-ia5     02-Jun-2020 01:45                3143
ber01-VHDL13_DWOG_020300-2006020300-dsw--0-ia5     02-Jun-2020 03:00                3144
ber01-VHDL13_DWOG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:15                3488
ber01-VHDL13_DWOG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:00                3841
ber01-VHDL13_DWOG_021700-2006021700-dsw--0-ia5     02-Jun-2020 17:30                3456
ber01-VHDL13_DWOG_030100-2006030100-dsw--0-ia5     03-Jun-2020 01:45                3308
ber01-VHDL13_DWOG_030300-2006030300-dsw--0-ia5     03-Jun-2020 03:17                3287
ber01-VHDL13_DWOG_030300_COR-2006030300-dsw--0-ia5 03-Jun-2020 02:05                3351
ber01-VHDL13_DWOG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:15                3763
ber01-VHDL13_DWOG_030800_COR-2006030800-dsw--0-ia5 03-Jun-2020 09:06                3784
ber01-VHDL13_DWOG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:00                3811
ber01-VHDL13_DWOH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:28                2157
ber01-VHDL13_DWOH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:28                2610
ber01-VHDL13_DWOH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:58                2503
ber01-VHDL13_DWOH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:28                2977
ber01-VHDL13_DWOH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:28                3226
ber01-VHDL13_DWOH_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:28                3427
ber01-VHDL13_DWOH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:28                3402
ber01-VHDL13_DWOH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:28                3416
ber01-VHDL13_DWOH_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:16                3306
ber01-VHDL13_DWOH_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 05:15                3310
ber01-VHDL13_DWOH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:28                3496
ber01-VHDL13_DWOH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:28                3531
ber01-VHDL13_DWOH_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:28                3743
ber01-VHDL13_DWOI_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:28                2084
ber01-VHDL13_DWOI_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:28                2505
ber01-VHDL13_DWOI_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:58                2412
ber01-VHDL13_DWOI_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:28                2724
ber01-VHDL13_DWOI_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:28                3089
ber01-VHDL13_DWOI_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:28                3297
ber01-VHDL13_DWOI_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:28                3416
ber01-VHDL13_DWOI_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:28                3484
ber01-VHDL13_DWOI_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:16                3449
ber01-VHDL13_DWOI_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 05:15                3453
ber01-VHDL13_DWOI_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:28                3665
ber01-VHDL13_DWOI_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:28                3652
ber01-VHDL13_DWOI_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:28                3867
ber01-VHDL13_DWON_011743-2006011743-dsw--0-ia5     01-Jun-2020 17:43                2939
ber01-VHDL13_DWON_011745-2006011745-dsw--0-ia5     01-Jun-2020 17:45                2939
ber01-VHDL13_DWON_011902-2006011902-dsw--0-ia5     01-Jun-2020 19:03                3063
ber01-VHDL13_DWON_011905-2006011905-dsw--0-ia5     01-Jun-2020 19:05                3124
ber01-VHDL13_DWON_012124-2006012124-dsw--0-ia5     01-Jun-2020 21:24                3124
ber01-VHDL13_DWON_012126-2006012126-dsw--0-ia5     01-Jun-2020 21:26                3124
ber01-VHDL13_DWON_020059-2006020059-dsw--0-ia5     02-Jun-2020 00:59                3406
ber01-VHDL13_DWON_020103-2006020103-dsw--0-ia5     02-Jun-2020 01:03                3521
ber01-VHDL13_DWON_020104-2006020104-dsw--0-ia5     02-Jun-2020 01:04                3521
ber01-VHDL13_DWON_020240-2006020240-dsw--0-ia5     02-Jun-2020 02:40                3523
ber01-VHDL13_DWON_020514-2006020514-dsw--0-ia5     02-Jun-2020 05:14                3567
ber01-VHDL13_DWON_020728-2006020728-dsw--0-ia5     02-Jun-2020 07:28                3937
ber01-VHDL13_DWON_021123-2006021123-dsw--0-ia5     02-Jun-2020 11:23                3948
ber01-VHDL13_DWON_021457-2006021457-dsw--0-ia5     02-Jun-2020 14:57                3942
ber01-VHDL13_DWON_021459-2006021459-dsw--0-ia5     02-Jun-2020 14:59                4055
ber01-VHDL13_DWON_021655-2006021655-dsw--0-ia5     02-Jun-2020 16:55                3523
ber01-VHDL13_DWON_021701-2006021701-dsw--0-ia5     02-Jun-2020 17:01                3482
ber01-VHDL13_DWON_021754-2006021754-dsw--0-ia5     02-Jun-2020 17:54                3538
ber01-VHDL13_DWON_022029-2006022029-dsw--0-ia5     02-Jun-2020 20:29                3380
ber01-VHDL13_DWON_030142-2006030142-dsw--0-ia5     03-Jun-2020 01:42                3111
ber01-VHDL13_DWON_030159-2006030159-dsw--0-ia5     03-Jun-2020 02:00                3071
ber01-VHDL13_DWON_030248-2006030248-dsw--0-ia5     03-Jun-2020 02:48                3071
ber01-VHDL13_DWON_030516-2006030516-dsw--0-ia5     03-Jun-2020 05:16                3550
ber01-VHDL13_DWON_030517-2006030517-dsw--0-ia5     03-Jun-2020 05:17                3550
ber01-VHDL13_DWON_030716-2006030716-dsw--0-ia5     03-Jun-2020 07:16                3785
ber01-VHDL13_DWON_030751-2006030751-dsw--0-ia5     03-Jun-2020 07:51                3782
ber01-VHDL13_DWON_030804-2006030804-dsw--0-ia5     03-Jun-2020 08:04                3782
ber01-VHDL13_DWON_031109-2006031109-dsw--0-ia5     03-Jun-2020 11:09                3683
ber01-VHDL13_DWON_031407-2006031407-dsw--0-ia5     03-Jun-2020 14:07                3887
ber01-VHDL13_DWPG_011730-2006011730-dsw--0-ia5     01-Jun-2020 17:30                2233
ber01-VHDL13_DWPG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                2151
ber01-VHDL13_DWPG_011930-2006011930-dsw--0-ia5     01-Jun-2020 19:30                2150
ber01-VHDL13_DWPG_012030-2006012030-dsw--0-ia5     01-Jun-2020 20:30                2150
ber01-VHDL13_DWPG_020030-2006020030-dsw--0-ia5     02-Jun-2020 00:30                2569
ber01-VHDL13_DWPG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2560
ber01-VHDL13_DWPG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2606
ber01-VHDL13_DWPG_020530-2006020530-dsw--0-ia5     02-Jun-2020 05:30                2604
ber01-VHDL13_DWPG_020630-2006020630-dsw--0-ia5     02-Jun-2020 06:30                2606
ber01-VHDL13_DWPG_020730-2006020730-dsw--0-ia5     02-Jun-2020 07:30                2677
ber01-VHDL13_DWPG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2648
ber01-VHDL13_DWPG_020930-2006020930-dsw--0-ia5     02-Jun-2020 09:30                2647
ber01-VHDL13_DWPG_021030-2006021030-dsw--0-ia5     02-Jun-2020 10:30                2647
ber01-VHDL13_DWPG_021130-2006021130-dsw--0-ia5     02-Jun-2020 11:30                2646
ber01-VHDL13_DWPG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                3105
ber01-VHDL13_DWPG_021330-2006021330-dsw--0-ia5     02-Jun-2020 13:30                3176
ber01-VHDL13_DWPG_021430-2006021430-dsw--0-ia5     02-Jun-2020 14:30                3237
ber01-VHDL13_DWPG_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:30                2999
ber01-VHDL13_DWPG_021630-2006021630-dsw--0-ia5     02-Jun-2020 16:30                2998
ber01-VHDL13_DWPG_021730-2006021730-dsw--0-ia5     02-Jun-2020 17:30                2934
ber01-VHDL13_DWPG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2989
ber01-VHDL13_DWPG_021930-2006021930-dsw--0-ia5     02-Jun-2020 19:30                2988
ber01-VHDL13_DWPG_022030-2006022030-dsw--0-ia5     02-Jun-2020 20:30                2988
ber01-VHDL13_DWPG_030030-2006030030-dsw--0-ia5     03-Jun-2020 00:30                3157
ber01-VHDL13_DWPG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3230
ber01-VHDL13_DWPG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3231
ber01-VHDL13_DWPG_030530-2006030530-dsw--0-ia5     03-Jun-2020 05:30                3257
ber01-VHDL13_DWPG_030630-2006030630-dsw--0-ia5     03-Jun-2020 06:30                3624
ber01-VHDL13_DWPG_030730-2006030730-dsw--0-ia5     03-Jun-2020 07:30                3624
ber01-VHDL13_DWPG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3666
ber01-VHDL13_DWPG_030800_COR-2006030800-dsw--0-ia5 03-Jun-2020 09:21                3681
ber01-VHDL13_DWPG_030930-2006030930-dsw--0-ia5     03-Jun-2020 09:30                3680
ber01-VHDL13_DWPG_031030-2006031030-dsw--0-ia5     03-Jun-2020 10:30                3694
ber01-VHDL13_DWPG_031130-2006031130-dsw--0-ia5     03-Jun-2020 11:30                3690
ber01-VHDL13_DWPG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3693
ber01-VHDL13_DWPG_031330-2006031330-dsw--0-ia5     03-Jun-2020 13:30                3692
ber01-VHDL13_DWPG_031430-2006031430-dsw--0-ia5     03-Jun-2020 14:30                3563
ber01-VHDL13_DWPG_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                3569
ber01-VHDL13_DWPG_031630-2006031630-dsw--0-ia5     03-Jun-2020 16:30                3568
ber01-VHDL13_DWPH_011730-2006011730-dsw--0-ia5     01-Jun-2020 17:30                2177
ber01-VHDL13_DWPH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                2013
ber01-VHDL13_DWPH_011930-2006011930-dsw--0-ia5     01-Jun-2020 19:30                2013
ber01-VHDL13_DWPH_012030-2006012030-dsw--0-ia5     01-Jun-2020 20:30                2013
ber01-VHDL13_DWPH_020030-2006020030-dsw--0-ia5     02-Jun-2020 00:30                2231
ber01-VHDL13_DWPH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2231
ber01-VHDL13_DWPH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2231
ber01-VHDL13_DWPH_020530-2006020530-dsw--0-ia5     02-Jun-2020 05:30                2231
ber01-VHDL13_DWPH_020630-2006020630-dsw--0-ia5     02-Jun-2020 06:30                2286
ber01-VHDL13_DWPH_020730-2006020730-dsw--0-ia5     02-Jun-2020 07:30                2311
ber01-VHDL13_DWPH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2304
ber01-VHDL13_DWPH_020930-2006020930-dsw--0-ia5     02-Jun-2020 09:30                2304
ber01-VHDL13_DWPH_021030-2006021030-dsw--0-ia5     02-Jun-2020 10:30                2304
ber01-VHDL13_DWPH_021130-2006021130-dsw--0-ia5     02-Jun-2020 11:30                2304
ber01-VHDL13_DWPH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                2816
ber01-VHDL13_DWPH_021330-2006021330-dsw--0-ia5     02-Jun-2020 13:30                2743
ber01-VHDL13_DWPH_021430-2006021430-dsw--0-ia5     02-Jun-2020 14:30                2906
ber01-VHDL13_DWPH_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:30                3001
ber01-VHDL13_DWPH_021630-2006021630-dsw--0-ia5     02-Jun-2020 16:30                3001
ber01-VHDL13_DWPH_021730-2006021730-dsw--0-ia5     02-Jun-2020 17:30                2908
ber01-VHDL13_DWPH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2915
ber01-VHDL13_DWPH_021930-2006021930-dsw--0-ia5     02-Jun-2020 19:30                2915
ber01-VHDL13_DWPH_022030-2006022030-dsw--0-ia5     02-Jun-2020 20:30                2915
ber01-VHDL13_DWPH_030030-2006030030-dsw--0-ia5     03-Jun-2020 00:30                3040
ber01-VHDL13_DWPH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3158
ber01-VHDL13_DWPH_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3158
ber01-VHDL13_DWPH_030530-2006030530-dsw--0-ia5     03-Jun-2020 05:30                3708
ber01-VHDL13_DWPH_030630-2006030630-dsw--0-ia5     03-Jun-2020 06:30                3703
ber01-VHDL13_DWPH_030730-2006030730-dsw--0-ia5     03-Jun-2020 07:30                3703
ber01-VHDL13_DWPH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3577
ber01-VHDL13_DWPH_030930-2006030930-dsw--0-ia5     03-Jun-2020 09:30                3586
ber01-VHDL13_DWPH_031030-2006031030-dsw--0-ia5     03-Jun-2020 10:30                3602
ber01-VHDL13_DWPH_031130-2006031130-dsw--0-ia5     03-Jun-2020 11:30                3576
ber01-VHDL13_DWPH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3608
ber01-VHDL13_DWPH_031330-2006031330-dsw--0-ia5     03-Jun-2020 13:30                3608
ber01-VHDL13_DWPH_031430-2006031430-dsw--0-ia5     03-Jun-2020 14:30                3608
ber01-VHDL13_DWPH_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                3565
ber01-VHDL13_DWPH_031630-2006031630-dsw--0-ia5     03-Jun-2020 16:30                3565
ber01-VHDL13_DWSG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1829
ber01-VHDL13_DWSG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2161
ber01-VHDL13_DWSG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2658
ber01-VHDL13_DWSG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2919
ber01-VHDL13_DWSG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:30                2842
ber01-VHDL13_DWSG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2880
ber01-VHDL13_DWSG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3716
ber01-VHDL13_DWSG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3863
ber01-VHDL13_DWSG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3901
ber01-VHDL13_DWSG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3921
ber01-VHDL13_DWSN_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1668
ber01-VHDL13_DWSN_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                1937
ber01-VHDL13_DWSN_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                1936
ber01-VHDL13_DWSN_020400_COR-2006020400-dsw--0-ia5 02-Jun-2020 05:11                2422
ber01-VHDL13_DWSN_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2469
ber01-VHDL13_DWSN_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2347
ber01-VHDL13_DWSN_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2255
ber01-VHDL13_DWSN_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2557
ber01-VHDL13_DWSN_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                2808
ber01-VHDL13_DWSN_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                2749
ber01-VHDL13_DWSN_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                2845
ber01-VHDL13_DWSO_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1784
ber01-VHDL13_DWSO_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2127
ber01-VHDL13_DWSO_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2126
ber01-VHDL13_DWSO_020400_COR-2006020400-dsw--0-ia5 02-Jun-2020 05:11                2600
ber01-VHDL13_DWSO_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2860
ber01-VHDL13_DWSO_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2685
ber01-VHDL13_DWSO_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2677
ber01-VHDL13_DWSO_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3103
ber01-VHDL13_DWSO_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3472
ber01-VHDL13_DWSO_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3422
ber01-VHDL13_DWSO_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                3586
ber01-VHDL13_DWSP_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:30                1845
ber01-VHDL13_DWSP_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2156
ber01-VHDL13_DWSP_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:30                2155
ber01-VHDL13_DWSP_020400_COR-2006020400-dsw--0-ia5 02-Jun-2020 05:11                2613
ber01-VHDL13_DWSP_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:30                2719
ber01-VHDL13_DWSP_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:30                2504
ber01-VHDL13_DWSP_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                2458
ber01-VHDL13_DWSP_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                2745
ber01-VHDL13_DWSP_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3067
ber01-VHDL13_DWSP_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3028
ber01-VHDL13_DWSP_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:30                3149
ber01-VHDL17_DWOG_021200-2006021200-dsw--0-ia5     02-Jun-2020 12:15                2300
ber01-VHDL17_DWOG_031200-2006031200-dsw--0-ia5     03-Jun-2020 10:59                2692
ber01-VHDL20_DWHG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2112
ber01-VHDL20_DWHG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2259
ber01-VHDL20_DWHG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:45                2270
ber01-VHDL20_DWHG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                2498
ber01-VHDL20_DWHG_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:45                2857
ber01-VHDL20_DWHG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                2651
ber01-VHDL20_DWHG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                2991
ber01-VHDL20_DWHG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:45                3047
ber01-VHDL20_DWHG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:45                3164
ber01-VHDL20_DWHG_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:45                3261
ber01-VHDL20_DWHG_031300_COR-2006031300-dsw--0-ia5 03-Jun-2020 14:06                3291
ber01-VHDL20_DWHH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2245
ber01-VHDL20_DWHH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2417
ber01-VHDL20_DWHH_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:45                2432
ber01-VHDL20_DWHH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                2574
ber01-VHDL20_DWHH_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:45                2696
ber01-VHDL20_DWHH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                2531
ber01-VHDL20_DWHH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                2955
ber01-VHDL20_DWHH_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:45                2990
ber01-VHDL20_DWHH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:45                3352
ber01-VHDL20_DWHH_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:45                3459
ber01-VHDL20_DWHH_031300_COR-2006031300-dsw--0-ia5 03-Jun-2020 15:22                3501
gts01-VHDL12_DWON_011815-2006011745-afsv--61-ia5   01-Jun-2020 17:45                2392
gts01-VHDL12_DWON_020115-2006020145-afsv--10-ia5   02-Jun-2020 01:45                3167
gts01-VHDL12_DWON_020530-2006020530-afsv--21-ia5   02-Jun-2020 05:30                3215
gts01-VHDL12_DWON_020815-2006020815-afsv--94-ia5   02-Jun-2020 08:15                3568
gts01-VHDL12_DWON_021330-2006021230-afsv--33-ia5   02-Jun-2020 12:30                3576
gts01-VHDL12_DWON_021815-2006021745-afsv--87-ia5   02-Jun-2020 17:45                3096
gts01-VHDL12_DWON_030115-2006030145-afsv--14-ia5   03-Jun-2020 01:45                2792
gts01-VHDL12_DWON_030115_COR-2006030205-afsv--2..> 03-Jun-2020 02:05                2756
gts01-VHDL12_DWON_030530-2006030530-afsv--54-ia5   03-Jun-2020 05:30                3250
gts01-VHDL12_DWON_030815-2006030815-afsv--42-ia5   03-Jun-2020 08:15                3487
gts01-VHDL12_DWON_031330-2006031230-afsv--85-ia5   03-Jun-2020 12:30                3386
pid-VHDL12_DWEH_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:28                2230
pid-VHDL12_DWEH_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:28                3172
pid-VHDL12_DWHG_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1788
pid-VHDL12_DWHG_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                1798
pid-VHDL12_DWHG_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2470
pid-VHDL12_DWHG_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2521
pid-VHDL12_DWHH_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1941
pid-VHDL12_DWHH_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                1956
pid-VHDL12_DWHH_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2392
pid-VHDL12_DWHH_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2424
pid-VHDL12_DWLG_011800-2006011800-dsw--0-ia5       01-Jun-2020 18:30                1364
pid-VHDL12_DWLG_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                2135
pid-VHDL12_DWLG_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                2170
pid-VHDL12_DWLG_020800-2006020800-dsw--0-ia5       02-Jun-2020 08:30                2153
pid-VHDL12_DWLG_021300-2006021300-dsw--0-ia5       02-Jun-2020 12:30                2125
pid-VHDL12_DWLG_021800-2006021800-dsw--0-ia5       02-Jun-2020 18:30                2013
pid-VHDL12_DWLG_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2267
pid-VHDL12_DWLG_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2366
pid-VHDL12_DWLG_030800-2006030800-dsw--0-ia5       03-Jun-2020 08:30                2363
pid-VHDL12_DWLG_031300-2006031300-dsw--0-ia5       03-Jun-2020 12:30                2326
pid-VHDL12_DWLH_011800-2006011800-dsw--0-ia5       01-Jun-2020 18:30                1272
pid-VHDL12_DWLH_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1657
pid-VHDL12_DWLH_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                1623
pid-VHDL12_DWLH_020800-2006020800-dsw--0-ia5       02-Jun-2020 08:30                1623
pid-VHDL12_DWLH_021300-2006021300-dsw--0-ia5       02-Jun-2020 12:30                1570
pid-VHDL12_DWLH_021800-2006021800-dsw--0-ia5       02-Jun-2020 18:30                1799
pid-VHDL12_DWLH_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2184
pid-VHDL12_DWLH_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2247
pid-VHDL12_DWLH_030800-2006030800-dsw--0-ia5       03-Jun-2020 08:30                2273
pid-VHDL12_DWLH_031300-2006031300-dsw--0-ia5       03-Jun-2020 12:30                2249
pid-VHDL12_DWLI_011800-2006011800-dsw--0-ia5       01-Jun-2020 18:30                1270
pid-VHDL12_DWLI_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1654
pid-VHDL12_DWLI_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                1628
pid-VHDL12_DWLI_020800-2006020800-dsw--0-ia5       02-Jun-2020 08:30                1628
pid-VHDL12_DWLI_021300-2006021300-dsw--0-ia5       02-Jun-2020 12:30                1584
pid-VHDL12_DWLI_021800-2006021800-dsw--0-ia5       02-Jun-2020 18:30                1799
pid-VHDL12_DWLI_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2182
pid-VHDL12_DWLI_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2249
pid-VHDL12_DWLI_030800-2006030800-dsw--0-ia5       03-Jun-2020 08:30                2275
pid-VHDL12_DWLI_031300-2006031300-dsw--0-ia5       03-Jun-2020 12:30                2251
pid-VHDL12_DWMG_011800-2006011800-dsw--0-ia5       01-Jun-2020 18:30                1345
pid-VHDL12_DWMG_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1723
pid-VHDL12_DWMG_020400-2006020400-dsw--0-ia5       02-Jun-2020 04:30                1745
pid-VHDL12_DWMG_020800-2006020800-dsw--0-ia5       02-Jun-2020 08:30                1867
pid-VHDL12_DWMG_021300-2006021300-dsw--0-ia5       02-Jun-2020 12:30                2311
pid-VHDL12_DWMG_021800-2006021800-dsw--0-ia5       02-Jun-2020 18:30                1887
pid-VHDL12_DWMG_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                2138
pid-VHDL12_DWMG_030400-2006030400-dsw--0-ia5       03-Jun-2020 04:30                2136
pid-VHDL12_DWMG_030800-2006030800-dsw--0-ia5       03-Jun-2020 08:30                2484
pid-VHDL12_DWMG_031300-2006031300-dsw--0-ia5       03-Jun-2020 12:30                2439
pid-VHDL12_DWOG_020100-2006020100-dsw--0-ia5       02-Jun-2020 01:45                2702
pid-VHDL12_DWOG_020300-2006020300-dsw--0-ia5       02-Jun-2020 03:00                2703
pid-VHDL12_DWOG_030100-2006030100-dsw--0-ia5       03-Jun-2020 01:45                2913
pid-VHDL12_DWOG_030300-2006030300-dsw--0-ia5       03-Jun-2020 03:00                2892
pid-VHDL12_DWOH_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:28                2245
pid-VHDL12_DWOH_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:28                3001
pid-VHDL12_DWOI_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:28                2129
pid-VHDL12_DWOI_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:28                3063
pid-VHDL12_DWSG_020200-2006020200-dsw--0-ia5       02-Jun-2020 02:30                1749
pid-VHDL12_DWSG_030200-2006030200-dsw--0-ia5       03-Jun-2020 02:30                3111
swis2-VHDL20_DWEG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2370
swis2-VHDL20_DWEG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2770
swis2-VHDL20_DWEG_020400-2006020400-dsw--0-ia5     02-Jun-2020 05:15                2710
swis2-VHDL20_DWEG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                3184
swis2-VHDL20_DWEG_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:45                3443
swis2-VHDL20_DWEG_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:45                3634
swis2-VHDL20_DWEG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                3615
swis2-VHDL20_DWEG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                3576
swis2-VHDL20_DWEG_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:15                3513
swis2-VHDL20_DWEG_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 05:15                3795
swis2-VHDL20_DWEG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:45                3703
swis2-VHDL20_DWEG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:45                3754
swis2-VHDL20_DWEG_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:45                3950
swis2-VHDL20_DWEH_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2328
swis2-VHDL20_DWEH_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2787
swis2-VHDL20_DWEH_020400-2006020400-dsw--0-ia5     02-Jun-2020 05:15                2678
swis2-VHDL20_DWEH_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                3262
swis2-VHDL20_DWEH_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:45                3440
swis2-VHDL20_DWEH_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:45                3643
swis2-VHDL20_DWEH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                3665
swis2-VHDL20_DWEH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                3782
swis2-VHDL20_DWEH_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:15                3689
swis2-VHDL20_DWEH_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 05:15                4001
swis2-VHDL20_DWEH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:45                3713
swis2-VHDL20_DWEH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:45                3817
swis2-VHDL20_DWEH_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:45                4000
swis2-VHDL20_DWEI_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2297
swis2-VHDL20_DWEI_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2666
swis2-VHDL20_DWEI_020400-2006020400-dsw--0-ia5     02-Jun-2020 05:15                2625
swis2-VHDL20_DWEI_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                2931
swis2-VHDL20_DWEI_021300-2006021300-dsw--0-ia5     02-Jun-2020 12:45                3302
swis2-VHDL20_DWEI_021500-2006021500-dsw--0-ia5     02-Jun-2020 15:45                3510
swis2-VHDL20_DWEI_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                3629
swis2-VHDL20_DWEI_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                3645
swis2-VHDL20_DWEI_030400-2006030400-dsw--0-ia5     03-Jun-2020 05:15                3662
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swis2-VHDL20_DWPG_012030-2006012030-dsw--0-ia5     01-Jun-2020 20:30                2337
swis2-VHDL20_DWPG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:30                2747
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swis2-VHDL20_DWPG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3417
swis2-VHDL20_DWPG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3416
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swis2-VHDL20_DWPG_031130-2006031130-dsw--0-ia5     03-Jun-2020 11:30                3877
swis2-VHDL20_DWPG_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3879
swis2-VHDL20_DWPG_031330-2006031330-dsw--0-ia5     03-Jun-2020 13:30                3879
swis2-VHDL20_DWPG_031430-2006031430-dsw--0-ia5     03-Jun-2020 14:30                3750
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swis2-VHDL20_DWPH_021430-2006021430-dsw--0-ia5     02-Jun-2020 14:30                3093
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swis2-VHDL20_DWPH_021630-2006021630-dsw--0-ia5     02-Jun-2020 16:30                3188
swis2-VHDL20_DWPH_021730-2006021730-dsw--0-ia5     02-Jun-2020 17:30                3095
swis2-VHDL20_DWPH_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:30                3102
swis2-VHDL20_DWPH_021930-2006021930-dsw--0-ia5     02-Jun-2020 19:30                3102
swis2-VHDL20_DWPH_022030-2006022030-dsw--0-ia5     02-Jun-2020 20:30                3102
swis2-VHDL20_DWPH_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:30                3345
swis2-VHDL20_DWPH_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:30                3345
swis2-VHDL20_DWPH_030400_COR-2006030400-dsw--0-ia5 03-Jun-2020 04:55                3714
swis2-VHDL20_DWPH_030530-2006030530-dsw--0-ia5     03-Jun-2020 05:30                3895
swis2-VHDL20_DWPH_030630-2006030630-dsw--0-ia5     03-Jun-2020 06:30                3890
swis2-VHDL20_DWPH_030730-2006030730-dsw--0-ia5     03-Jun-2020 07:30                3890
swis2-VHDL20_DWPH_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:30                3764
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swis2-VHDL20_DWPH_031030-2006031030-dsw--0-ia5     03-Jun-2020 10:30                3789
swis2-VHDL20_DWPH_031130-2006031130-dsw--0-ia5     03-Jun-2020 11:30                3763
swis2-VHDL20_DWPH_031300-2006031300-dsw--0-ia5     03-Jun-2020 12:30                3795
swis2-VHDL20_DWPH_031330-2006031330-dsw--0-ia5     03-Jun-2020 13:30                3795
swis2-VHDL20_DWPH_031430-2006031430-dsw--0-ia5     03-Jun-2020 14:30                3795
swis2-VHDL20_DWPH_031500-2006031500-dsw--0-ia5     03-Jun-2020 15:30                3752
swis2-VHDL20_DWPH_031630-2006031630-dsw--0-ia5     03-Jun-2020 16:30                3752
swis2-VHDL20_DWSG_011800-2006011800-dsw--0-ia5     01-Jun-2020 18:45                2061
swis2-VHDL20_DWSG_020200-2006020200-dsw--0-ia5     02-Jun-2020 02:45                2395
swis2-VHDL20_DWSG_020400-2006020400-dsw--0-ia5     02-Jun-2020 04:45                2901
swis2-VHDL20_DWSG_020800-2006020800-dsw--0-ia5     02-Jun-2020 08:45                3149
swis2-VHDL20_DWSG_021300-2006021300-dsw--0-ia5     02-Jun-2020 13:45                3149
swis2-VHDL20_DWSG_021800-2006021800-dsw--0-ia5     02-Jun-2020 18:45                3112
swis2-VHDL20_DWSG_030200-2006030200-dsw--0-ia5     03-Jun-2020 02:45                3950
swis2-VHDL20_DWSG_030400-2006030400-dsw--0-ia5     03-Jun-2020 04:45                4094
swis2-VHDL20_DWSG_030800-2006030800-dsw--0-ia5     03-Jun-2020 08:45                4131
swis2-VHDL20_DWSG_031300-2006031300-dsw--0-ia5     03-Jun-2020 13:45                4153
wst04-VHDL20_DWEG_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              241630
wst04-VHDL20_DWEG_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              242261
wst04-VHDL20_DWEG_020400-2006020400-omedes--0.pdf  02-Jun-2020 05:15              242517
wst04-VHDL20_DWEG_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              249319
wst04-VHDL20_DWEG_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              249423
wst04-VHDL20_DWEG_021500-2006021500-omedes--0.pdf  02-Jun-2020 15:45              249699
wst04-VHDL20_DWEG_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              248996
wst04-VHDL20_DWEG_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              248470
wst04-VHDL20_DWEG_030400-2006030400-omedes--0.pdf  03-Jun-2020 05:15              248978
wst04-VHDL20_DWEG_030400_COR-2006030400-omedes-..> 03-Jun-2020 05:15              248978
wst04-VHDL20_DWEG_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              252123
wst04-VHDL20_DWEG_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              252239
wst04-VHDL20_DWEG_031500-2006031500-omedes--0.pdf  03-Jun-2020 15:45              252330
wst04-VHDL20_DWEH_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              242863
wst04-VHDL20_DWEH_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              244173
wst04-VHDL20_DWEH_020400-2006020400-omedes--0.pdf  02-Jun-2020 05:15              243769
wst04-VHDL20_DWEH_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              244962
wst04-VHDL20_DWEH_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              245134
wst04-VHDL20_DWEH_021500-2006021500-omedes--0.pdf  02-Jun-2020 15:45              244783
wst04-VHDL20_DWEH_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              244700
wst04-VHDL20_DWEH_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              245393
wst04-VHDL20_DWEH_030400-2006030400-omedes--0.pdf  03-Jun-2020 05:15              244746
wst04-VHDL20_DWEH_030400_COR-2006030400-omedes-..> 03-Jun-2020 05:15              244746
wst04-VHDL20_DWEH_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              247886
wst04-VHDL20_DWEH_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              247862
wst04-VHDL20_DWEH_031500-2006031500-omedes--0.pdf  03-Jun-2020 15:45              248600
wst04-VHDL20_DWEI_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              332367
wst04-VHDL20_DWEI_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              333543
wst04-VHDL20_DWEI_020400-2006020400-omedes--0.pdf  02-Jun-2020 05:15              332814
wst04-VHDL20_DWEI_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              338967
wst04-VHDL20_DWEI_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              339226
wst04-VHDL20_DWEI_021500-2006021500-omedes--0.pdf  02-Jun-2020 15:45              339302
wst04-VHDL20_DWEI_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              338801
wst04-VHDL20_DWEI_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              338895
wst04-VHDL20_DWEI_030400-2006030400-omedes--0.pdf  03-Jun-2020 05:15              338937
wst04-VHDL20_DWEI_030400_COR-2006030400-omedes-..> 03-Jun-2020 05:15              338937
wst04-VHDL20_DWEI_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              345753
wst04-VHDL20_DWEI_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              345773
wst04-VHDL20_DWEI_031500-2006031500-omedes--0.pdf  03-Jun-2020 15:45              345859
wst04-VHDL20_DWHG_011800-2006011800-oflxs888--0..> 01-Jun-2020 18:45              343250
wst04-VHDL20_DWHG_020200-2006020200-oflxs888--0..> 02-Jun-2020 02:45              343746
wst04-VHDL20_DWHG_020400-2006020400-oflxs888--0..> 02-Jun-2020 04:45              343761
wst04-VHDL20_DWHG_020800-2006020800-oflxs888--0..> 02-Jun-2020 08:45              340512
wst04-VHDL20_DWHG_021300-2006021300-oflxs888--0..> 02-Jun-2020 13:45              341727
wst04-VHDL20_DWHG_021800-2006021800-oflxs888--0..> 02-Jun-2020 18:45              341529
wst04-VHDL20_DWHG_030200-2006030200-oflxs888--0..> 03-Jun-2020 02:45              342834
wst04-VHDL20_DWHG_030400-2006030400-oflxs888--0..> 03-Jun-2020 04:45              342813
wst04-VHDL20_DWHG_030800-2006030800-oflxs888--0..> 03-Jun-2020 08:45              339183
wst04-VHDL20_DWHG_031300-2006031300-oflxs888--0..> 03-Jun-2020 13:45              338305
wst04-VHDL20_DWHH_011800-2006011800-oflxs888--0..> 01-Jun-2020 18:45              330247
wst04-VHDL20_DWHH_020200-2006020200-oflxs888--0..> 02-Jun-2020 02:45              330166
wst04-VHDL20_DWHH_020400-2006020400-oflxs888--0..> 02-Jun-2020 04:45              330211
wst04-VHDL20_DWHH_020800-2006020800-oflxs888--0..> 02-Jun-2020 08:45              334513
wst04-VHDL20_DWHH_021300-2006021300-oflxs888--0..> 02-Jun-2020 13:45              335371
wst04-VHDL20_DWHH_021800-2006021800-oflxs888--0..> 02-Jun-2020 18:45              335233
wst04-VHDL20_DWHH_030200-2006030200-oflxs888--0..> 03-Jun-2020 02:45              336755
wst04-VHDL20_DWHH_030400-2006030400-oflxs888--0..> 03-Jun-2020 04:45              336803
wst04-VHDL20_DWHH_030800-2006030800-oflxs888--0..> 03-Jun-2020 08:45              338983
wst04-VHDL20_DWHH_031300-2006031300-oflxs888--0..> 03-Jun-2020 13:45              338295
wst04-VHDL20_DWLG_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:40              249118
wst04-VHDL20_DWLG_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:40              250398
wst04-VHDL20_DWLG_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:40              250652
wst04-VHDL20_DWLG_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:40              250236
wst04-VHDL20_DWLG_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:40              249908
wst04-VHDL20_DWLG_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:40              249921
wst04-VHDL20_DWLG_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:40              250503
wst04-VHDL20_DWLG_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:40              250793
wst04-VHDL20_DWLG_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:40              253120
wst04-VHDL20_DWLG_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:40              252605
wst04-VHDL20_DWLH_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:40              246565
wst04-VHDL20_DWLH_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:40              246774
wst04-VHDL20_DWLH_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:40              246907
wst04-VHDL20_DWLH_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:40              250296
wst04-VHDL20_DWLH_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:40              250001
wst04-VHDL20_DWLH_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:40              250871
wst04-VHDL20_DWLH_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:40              251706
wst04-VHDL20_DWLH_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:40              251498
wst04-VHDL20_DWLH_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:40              249322
wst04-VHDL20_DWLH_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:40              249326
wst04-VHDL20_DWLI_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:40              247257
wst04-VHDL20_DWLI_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:40              247436
wst04-VHDL20_DWLI_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:40              247643
wst04-VHDL20_DWLI_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:40              247281
wst04-VHDL20_DWLI_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:40              246972
wst04-VHDL20_DWLI_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:40              247871
wst04-VHDL20_DWLI_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:40              248664
wst04-VHDL20_DWLI_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:40              248525
wst04-VHDL20_DWLI_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:40              246460
wst04-VHDL20_DWLI_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:40              246467
wst04-VHDL20_DWMG_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              247115
wst04-VHDL20_DWMG_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              247936
wst04-VHDL20_DWMG_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:45              247393
wst04-VHDL20_DWMG_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              254193
wst04-VHDL20_DWMG_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              255794
wst04-VHDL20_DWMG_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              253372
wst04-VHDL20_DWMG_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              254115
wst04-VHDL20_DWMG_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:45              254090
wst04-VHDL20_DWMG_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              254772
wst04-VHDL20_DWMG_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              255463
wst04-VHDL20_DWMO_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              249435
wst04-VHDL20_DWMO_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              249941
wst04-VHDL20_DWMO_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:45              250455
wst04-VHDL20_DWMO_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              254158
wst04-VHDL20_DWMO_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              255186
wst04-VHDL20_DWMO_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              253628
wst04-VHDL20_DWMO_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              253776
wst04-VHDL20_DWMO_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:45              254717
wst04-VHDL20_DWMO_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              250045
wst04-VHDL20_DWMO_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              250048
wst04-VHDL20_DWMP_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              247030
wst04-VHDL20_DWMP_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              247310
wst04-VHDL20_DWMP_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:45              247405
wst04-VHDL20_DWMP_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              253962
wst04-VHDL20_DWMP_021300-2006021300-omedes--0.pdf  02-Jun-2020 12:45              255213
wst04-VHDL20_DWMP_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              253390
wst04-VHDL20_DWMP_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              253094
wst04-VHDL20_DWMP_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:45              253819
wst04-VHDL20_DWMP_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              255580
wst04-VHDL20_DWMP_031300-2006031300-omedes--0.pdf  03-Jun-2020 12:45              255571
wst04-VHDL20_DWPG_011730-2006011730-oflxs892--0..> 01-Jun-2020 17:30              345910
wst04-VHDL20_DWPG_011800-2006011800-oflxs892--0..> 01-Jun-2020 18:30              345863
wst04-VHDL20_DWPG_011930-2006011930-oflxs892--0..> 01-Jun-2020 19:30              345845
wst04-VHDL20_DWPG_012030-2006012030-oflxs892--0..> 01-Jun-2020 20:30              345845
wst04-VHDL20_DWPG_020200-2006020200-oflxs892--0..> 02-Jun-2020 02:30              346869
wst04-VHDL20_DWPG_020400-2006020400-oflxs892--0..> 02-Jun-2020 04:30              347340
wst04-VHDL20_DWPG_020530-2006020530-oflxs892--0..> 02-Jun-2020 05:30              347326
wst04-VHDL20_DWPG_020630-2006020630-oflxs892--0..> 02-Jun-2020 06:30              346671
wst04-VHDL20_DWPG_020730-2006020730-oflxs892--0..> 02-Jun-2020 07:30              346797
wst04-VHDL20_DWPG_020800-2006020800-oflxs892--0..> 02-Jun-2020 08:30              393558
wst04-VHDL20_DWPG_020930-2006020930-oflxs892--0..> 02-Jun-2020 09:30              348969
wst04-VHDL20_DWPG_021030-2006021030-oflxs892--0..> 02-Jun-2020 10:30              348969
wst04-VHDL20_DWPG_021130-2006021130-oflxs892--0..> 02-Jun-2020 11:30              348960
wst04-VHDL20_DWPG_021300-2006021300-oflxs892--0..> 02-Jun-2020 12:30              349188
wst04-VHDL20_DWPG_021330-2006021330-oflxs892--0..> 02-Jun-2020 13:30              349100
wst04-VHDL20_DWPG_021430-2006021430-oflxs892--0..> 02-Jun-2020 14:30              349119
wst04-VHDL20_DWPG_021500-2006021500-oflxs892--0..> 02-Jun-2020 15:30              349113
wst04-VHDL20_DWPG_021630-2006021630-oflxs892--0..> 02-Jun-2020 16:30              349101
wst04-VHDL20_DWPG_021730-2006021730-oflxs892--0..> 02-Jun-2020 17:30              349057
wst04-VHDL20_DWPG_021800-2006021800-oflxs892--0..> 02-Jun-2020 18:30              349076
wst04-VHDL20_DWPG_021930-2006021930-oflxs892--0..> 02-Jun-2020 19:30              349057
wst04-VHDL20_DWPG_022030-2006022030-oflxs892--0..> 02-Jun-2020 20:30              349057
wst04-VHDL20_DWPG_030200-2006030200-oflxs892--0..> 03-Jun-2020 02:30              349263
wst04-VHDL20_DWPG_030400-2006030400-oflxs892--0..> 03-Jun-2020 04:30              349235
wst04-VHDL20_DWPG_030400_COR-2006030400-oflxs89..> 03-Jun-2020 04:53              349241
wst04-VHDL20_DWPG_030530-2006030530-oflxs892--0..> 03-Jun-2020 05:30              349240
wst04-VHDL20_DWPG_030630-2006030630-oflxs892--0..> 03-Jun-2020 06:30              349722
wst04-VHDL20_DWPG_030730-2006030730-oflxs892--0..> 03-Jun-2020 07:30              349395
wst04-VHDL20_DWPG_030800-2006030800-oflxs892--0..> 03-Jun-2020 08:30              390355
wst04-VHDL20_DWPG_030930-2006030930-oflxs892--0..> 03-Jun-2020 09:30              346005
wst04-VHDL20_DWPG_031030-2006031030-oflxs892--0..> 03-Jun-2020 10:30              346021
wst04-VHDL20_DWPG_031130-2006031130-oflxs892--0..> 03-Jun-2020 11:30              345814
wst04-VHDL20_DWPG_031300-2006031300-oflxs892--0..> 03-Jun-2020 12:30              345895
wst04-VHDL20_DWPG_031330-2006031330-oflxs892--0..> 03-Jun-2020 13:30              345883
wst04-VHDL20_DWPG_031430-2006031430-oflxs892--0..> 03-Jun-2020 14:30              345786
wst04-VHDL20_DWPG_031500-2006031500-oflxs892--0..> 03-Jun-2020 15:30              345808
wst04-VHDL20_DWPG_031630-2006031630-oflxs892--0..> 03-Jun-2020 16:30              345789
wst04-VHDL20_DWPH_011730-2006011730-oflxs892--0..> 01-Jun-2020 17:30              247938
wst04-VHDL20_DWPH_011800-2006011800-oflxs892--0..> 01-Jun-2020 18:30              292415
wst04-VHDL20_DWPH_011930-2006011930-oflxs892--0..> 01-Jun-2020 19:30              247810
wst04-VHDL20_DWPH_012030-2006012030-oflxs892--0..> 01-Jun-2020 20:30              247810
wst04-VHDL20_DWPH_020200-2006020200-oflxs892--0..> 02-Jun-2020 02:30              248594
wst04-VHDL20_DWPH_020400-2006020400-oflxs892--0..> 02-Jun-2020 04:30              248610
wst04-VHDL20_DWPH_020530-2006020530-oflxs892--0..> 02-Jun-2020 05:30              248540
wst04-VHDL20_DWPH_020630-2006020630-oflxs892--0..> 02-Jun-2020 06:30              248059
wst04-VHDL20_DWPH_020730-2006020730-oflxs892--0..> 02-Jun-2020 07:30              248071
wst04-VHDL20_DWPH_020800-2006020800-oflxs892--0..> 02-Jun-2020 08:30              293920
wst04-VHDL20_DWPH_020930-2006020930-oflxs892--0..> 02-Jun-2020 09:30              249315
wst04-VHDL20_DWPH_021030-2006021030-oflxs892--0..> 02-Jun-2020 10:30              249315
wst04-VHDL20_DWPH_021130-2006021130-oflxs892--0..> 02-Jun-2020 11:30              249314
wst04-VHDL20_DWPH_021300-2006021300-oflxs892--0..> 02-Jun-2020 12:30              250181
wst04-VHDL20_DWPH_021330-2006021330-oflxs892--0..> 02-Jun-2020 13:30              250083
wst04-VHDL20_DWPH_021430-2006021430-oflxs892--0..> 02-Jun-2020 14:30              250189
wst04-VHDL20_DWPH_021500-2006021500-oflxs892--0..> 02-Jun-2020 15:30              250256
wst04-VHDL20_DWPH_021630-2006021630-oflxs892--0..> 02-Jun-2020 16:30              250235
wst04-VHDL20_DWPH_021730-2006021730-oflxs892--0..> 02-Jun-2020 17:30              250060
wst04-VHDL20_DWPH_021800-2006021800-oflxs892--0..> 02-Jun-2020 18:30              294562
wst04-VHDL20_DWPH_021930-2006021930-oflxs892--0..> 02-Jun-2020 19:30              249945
wst04-VHDL20_DWPH_022030-2006022030-oflxs892--0..> 02-Jun-2020 20:30              249945
wst04-VHDL20_DWPH_030200-2006030200-oflxs892--0..> 03-Jun-2020 02:30              250147
wst04-VHDL20_DWPH_030400-2006030400-oflxs892--0..> 03-Jun-2020 04:30              250171
wst04-VHDL20_DWPH_030400_COR-2006030400-oflxs89..> 03-Jun-2020 04:54              250431
wst04-VHDL20_DWPH_030530-2006030530-oflxs892--0..> 03-Jun-2020 05:30              250878
wst04-VHDL20_DWPH_030630-2006030630-oflxs892--0..> 03-Jun-2020 06:30              250502
wst04-VHDL20_DWPH_030730-2006030730-oflxs892--0..> 03-Jun-2020 07:30              250506
wst04-VHDL20_DWPH_030800-2006030800-oflxs892--0..> 03-Jun-2020 08:30              292324
wst04-VHDL20_DWPH_030930-2006030930-oflxs892--0..> 03-Jun-2020 09:30              247889
wst04-VHDL20_DWPH_031030-2006031030-oflxs892--0..> 03-Jun-2020 10:30              247880
wst04-VHDL20_DWPH_031130-2006031130-oflxs892--0..> 03-Jun-2020 11:30              247734
wst04-VHDL20_DWPH_031300-2006031300-oflxs892--0..> 03-Jun-2020 12:30              247843
wst04-VHDL20_DWPH_031330-2006031330-oflxs892--0..> 03-Jun-2020 13:30              247801
wst04-VHDL20_DWPH_031430-2006031430-oflxs892--0..> 03-Jun-2020 14:30              247801
wst04-VHDL20_DWPH_031500-2006031500-oflxs892--0..> 03-Jun-2020 15:30              247914
wst04-VHDL20_DWPH_031630-2006031630-oflxs892--0..> 03-Jun-2020 16:30              247905
wst04-VHDL20_DWSG_011800-2006011800-omedes--0.pdf  01-Jun-2020 18:45              248132
wst04-VHDL20_DWSG_020200-2006020200-omedes--0.pdf  02-Jun-2020 02:45              248277
wst04-VHDL20_DWSG_020400-2006020400-omedes--0.pdf  02-Jun-2020 04:45              249255
wst04-VHDL20_DWSG_020800-2006020800-omedes--0.pdf  02-Jun-2020 08:45              249238
wst04-VHDL20_DWSG_021300-2006021300-omedes--0.pdf  02-Jun-2020 13:45              249119
wst04-VHDL20_DWSG_021800-2006021800-omedes--0.pdf  02-Jun-2020 18:45              248517
wst04-VHDL20_DWSG_030200-2006030200-omedes--0.pdf  03-Jun-2020 02:45              249674
wst04-VHDL20_DWSG_030400-2006030400-omedes--0.pdf  03-Jun-2020 04:45              249842
wst04-VHDL20_DWSG_030800-2006030800-omedes--0.pdf  03-Jun-2020 08:45              251323
wst04-VHDL20_DWSG_031300-2006031300-omedes--0.pdf  03-Jun-2020 13:45              250970